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ACM Trans. Design Autom. Electr. Syst. 01/2010; 15.
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Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009; 01/2009
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IEEE Design & Test of Computers. 01/2009; 26:34-43.
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01/2009; Springer., ISBN: 978-1-4020-9364-7
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12/2008: pages 13-24;
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2008; 27:184-188.
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IEEE Computer. 01/2008; 41:47-54.
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Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008; 01/2008
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IEEE Trans. on CAD of Integrated Circuits and Systems. 01/2007; 26:152-165.
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8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA; 01/2007
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2007 International Conference on Computer-Aided Design (ICCAD'07), November 5-8, 2007, San Jose, CA, USA; 01/2007
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ACM Trans. Design Autom. Electr. Syst. 01/2007; 12.
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Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007; 01/2007
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Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007; 01/2007
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Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007; 01/2007
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2005 International Conference on Computer-Aided Design (ICCAD'05), November 6-10, 2005, San Jose, CA, USA; 01/2005
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2005 International Conference on Computer-Aided Design (ICCAD'05), November 6-10, 2005, San Jose, CA, USA; 01/2005
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ABSTRACT: Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the quality of the final design, often because they neglect important physical aspects of the layout, such as long wires or routing congestion. Our work defines and explores the concept of physical safeness and evaluates empirically its impact on route length, via count and timing. In addition, we propose a new physically safe and logically sound optimization, called SafeResynth, which provides immediately measurable improvements without altering the design's functionality. SafeResynth can enhance circuit timing without detrimental effects on route length and congestion. We achieve these improvements by performing a series of netlist transformations and re-placements that are individually evaluated for logical soundness (that is, they do not alter the logic functionality) and for physical safeness. When used alone, SafeResynth improves circuit delay of IWLS’05 benchmarks by 11% on average after routing, while increasing route length by less than 0.2%. Since transistors are not affected by SafeResynth, it can also be applied to post-silicon debugging, where only metal fixes are possible.
Integration, the VLSI Journal.
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ABSTRACT: The OpenAccess Gear package addresses several key tasks in syn-thesis, verification and layout of digital logic, and encourages syn-ergies between such optimizations. Primitives for logic simulation and equivalence-checking are particularly useful in both verifica-tion and logic synthesis, as exemplified by the AIG algorithms im-plemented in OAGear. We describe our re-design of simulation and equivalence-checking engines in OpenAccess Gear, and our empirical results show that our simulator runs 100 times faster on large netlists than the current implementation. To ensure a broad adoption of these core engines in the user community, we provided adequate GUI support using OAGear standard user interface.
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ABSTRACT: Traditional digital circuit synthesis flows start from an HDL be-havioral definition and assume that circuit functions are almost completely defined, making don't-care conditions rare. However, recent design methodologies do not always satisfy these assump-tions. For instance, third-party IP blocks used in a system-on-chip are often over-designed for the requirements at hand. By focusing only on the input combinations occurring in a specific application, one could resynthesize the system to greatly reduce its area and power consumption. Therefore we extend modern digital synthesis with a novel technique, called SWEDE, that makes use of exten-sive external don't-cares. Experiments indicate that SWEDE scales to large ICs with half-million input vectors and handles practical cases well.
