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ABSTRACT: HfTa-based oxide and oxynitride with or without Ta O <sub>x</sub> N <sub>y</sub> interlayer are fabricated on Ge substrate to form metal-oxide-semiconductor (MOS) capacitors. Their electrical properties and reliabilities are measured and compared. The results show that the MOS capacitor with a gate stack of HfTa-based oxynitride and thin Ta O <sub>x</sub> N <sub>y</sub> interlayer exhibits low interface-state/oxide-charge densities, low gate leakage, small hysteresis, small capacitance equivalent thickness (∼0.94 nm ) , and high dielectric constant (∼24) . All these should be attributed to the blocking role of the Ta O <sub>x</sub> N <sub>y</sub> interlayer against penetration of O into the Ge substrate and interdiffusions of Hf, Ge, and Ta, thus effectively suppressing the formation of unstable low- k Ge O <sub>x</sub> and giving a superior Ta O <sub>x</sub> N <sub>y</sub>/ Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric greatly improves device reliability through the formation of strong N-related bonds.
Applied Physics Letters 07/2008; · 3.84 Impact Factor
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Microelectronics Reliability. 01/2008; 48:181-186.
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Microelectronics Reliability. 01/2008; 48:693-697.
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Microelectronics Reliability. 01/2008; 48:23-28.
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ABSTRACT: Metal-oxide-semiconductor (MOS) capacitor with Hf Ti O N / Hf Si O N stack structure as high- k gate dielectric is fabricated, and its electrical properties are compared with those of a similar device with HfTiON only as gate dielectric. Experimental results show that the device with Hf Ti O N / Hf Si O N gate dielectric exhibits better interface properties, lower gate leakage current, and enhanced high-field reliability. All these improvements should be attributed to the fact that the HfSiON buffer layer effectively blocks the diffusion of Ti atoms to the Si substrate, thus resulting in a Si O <sub>2</sub>/ Si -like Hf Si O N / Si interface.
Applied Physics Letters 11/2007; · 3.84 Impact Factor
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ABSTRACT: In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.
Microelectronics Reliability.