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Publications (7)1.09 Total impact

  • Inhak Han, Youngsoo Shin
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    ABSTRACT: Dual edge-triggered flip-flop (DETFF) captures data at both clock edges. We observe that conventional sequential circuit that contains single edge-triggered flip-flops (SETFFs) can be simplified by identifying pairs of combinational subcircuits that are structurally identical, removing one subcircuit of each pair, and providing input data twice by using DETFFs where SETFFs have been used. The resulting circuit is named folded circuit. We carry the observation to technology mapping problem, so that many identical subcircuits are synthesized early on in the design process. Experimental results with some test circuits indicate that circuit area is reduced as much as 16%.
    IC Design & Technology (ICICDT), 2013 International Conference on; 01/2013
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    Inhak Han, Youngsoo Shin
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    ABSTRACT: Clock gating is typically dictated by designers in register transfer level (RTL). Automatic synthesis of clock gating in gate level has been less explored, but is certainly more convenient to designers; it can also complement RTL clock gating by extracting additional gating conditions. The key problem in gate-level clock gating synthesis is to implement gating conditions with minimum amount of additional logic. In this paper, we aim to utilize the existing combinational logic as much as possible. This is done by extracting a factored form (modeled by a factoring tree) of each gating condition, and try to cover the tree by factoring trees of existing combinational logic; the corresponding process is named factored form matching. Experiments demonstrate that the proposed matching achieves 25% reduction in the number of gates to implement gating conditions; this can be compared to prior method using Boolean division, which achieves 10% reduction.
    01/2012;
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    ABSTRACT: Pulsed-latch circuits, in which latches are triggered by a short pulse, can reduce power consumption as well as increasing performance; and they can largely be designed using conventional computer-aided design tools. We explore the automatic synthesis of clock-gating logic for pulsed-latch circuits in which gating is implemented by enabling and disabling several pulse generators. The key problem is to arrange that each group of latches contains physically close latches, so that a short pulse from a pulse generator is delivered safely, and to ensure that the latches in a group have similar Boolean gating conditions because their clock is gated and ungated together. The resulting gating conditions should be implemented using as little extra logic as possible; for this purpose we rely on Boolean division, with an internal node of existing logic being used as the divisor. The proposed clock gating synthesis is assessed in 45-nm technology.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2012; 31(7):1019-1030. · 1.09 Impact Factor
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    ABSTRACT: A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the product of Green's function and power density integrated over space. The correlation coefficient between thermal signature and temperature is shown to be quite high, more than 0.7 in many examples. A floorplanner that uses thermal signature is constructed and assessed using real design examples in 32-nm technology. It produces a floorplan whose maximum temperature is 11.4°C smaller than that of standard floorplan, on average, in reasonable amount of runtime.
    Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE; 07/2011
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    ABSTRACT: A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic while gating probability is not sacrificed too much. We also have to take account of proximity of latches, because a pulser, which is gated by merged gating function, and its latches have to be physically close for safe delivery of pulse. The heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed and assessed in terms of power saving and area using 45-nm technology.
    Proceedings of the 16th Asia South Pacific Design Automation Conference, ASP-DAC 2011, Yokohama, Japan, January 25-27, 2011; 01/2011
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    ABSTRACT: Monte Carlo (MC) method is convenient and robust to estimate timing yield of circuits under the influence of process variations. The important question in MC method is the number of samples while we assure a desired accuracy of yield estimate, which is often addressed using a rule of thumb. Minimum number of samples can be estimated via approximation by a normal distribution, but the provided number may be too small to be used in practice considering that target yield, which is used to derive the number, is unknown. Chebyshev's inequality has been used to derive a sample number, but the number is too large this time. We develop a new expression, which provides the sample number that is much closer to the minimum (3× to 8×) compared to the number provided by Chebyshev's inequality (5× to 15×). We also propose a simple node filtering algorithm, where we identify the nodes that are likely to affect timing yield; the simulation with each MC sample can handle only a fraction of circuit elements as a result. Reducing the number of MC samples and simulating only selected nodes together yield 27× to 125× speedup over standard MC method.
    IC Design and Technology (ICICDT), 2010 IEEE International Conference on; 07/2010