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EURASIP J. Adv. Sig. Proc. 01/2007; 2007.
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IEEE Transactions on Signal Processing. 01/2006; 54:3279-3290.
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ABSTRACT: This paper presents a technique that predicts the initial search direction for the flexible triangle search algorithm (FTS), which was introduced in previous work by the authors. The FTS algorithm is a fast block-matching algorithm for block-based motion estimation. In the FTS, a search triangle is used to find the best matching blocks between two frames through successive iterations. During the search, the triangle changes its direction and size using reflection, expansion, contraction, and translation operations. These operations provide the triangle with the necessary flexibility to perform coarse or fine search and to locate the best matching blocks while checking fewer search positions compared to most other search algorithms. Analysis of the FTS behavior showed that the proper selection of the starting triangle for the search reduces the required number of block-matching evaluations by directing the search earlier in the direction of the minimum. In this paper, a prediction-based FTS, the PFTS, is introduced. In the PFTS, a prediction step is added to obtain the initial triangle for the search. Simulation results indicate that the PFTS requires a smaller number of block matching operations than that of the FTS. In addition, the compression ratio was improved slightly while the visual quality of the reconstructed sequence remained the same compared to the FTS
Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada; 01/2006
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ABSTRACT: In this paper a hardware architecture for the implementation of the flexible triangle search algorithm (FTS) using FPGAs is proposed. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work, which can be used for video compression. The FTS finds the best matching blocks between two frames using a search triangle which changes its direction and size through a set of operations. These operations provide the triangle with the necessary flexibility to locate the best matching block. Simulation results indicate that the FTS reduces the number of block matching operations compared with other fast block matching algorithms without affecting quality or compression ratio of the compressed bitstream. In this paper, a hardware architecture for a FPGA implementation of the FTS algorithm is proposed. This architecture is simulated and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the full search (FS) algorithm. Results indicates that the FTS FPGA implementation requires less number of gates than FS and the required number of cycles needed to complete motion search for one block is much lower. This indicates that the proposed implementation is fast and requires less hardware and power than existing ones
International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan; 01/2005
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IEEE Transactions on Signal Processing. 01/2005; 53:945-956.
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01/2004
