David Blaauw

Concordia University–Ann Arbor, Ann Arbor, Michigan, United States

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Publications (452)221.81 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper explores the effectiveness of different knobs to dynamically trade energy consumption with output quality in approximate SRAMs for error-tolerant applications (such as video). Leveraging the different impact of errors on quality at most significant bit (MSB) and least significant bit (LSB) positions, energy savings higher than those provided by simple voltage scaling are enabled. Firstly, a comparison of two techniques, dual-𝑽𝑫𝑫 and LSB dropping, is carried out showing that the latter is preferable thanks to its intrinsic simplicity and more pronounced energy savings. Secondly, a selective Error Correction Code (ECC) technique which reuses the LSBs as check bits to protect MSBs is investigated. Measurements on a 28nm CMOS 32kb SRAM show that bit dropping and bit reuse achieve an energy reduction of up to 33% and 28%, compared to simple voltage scaling at iso-quality. When combined together, the two techniques achieve a better energy saving (40%) and a supply voltage reduction of about 100mV at iso-quality. Finally, guidelines to select the energy-optimal combination of the two techniques are provided for a given quality target.
    International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS); 09/2015
  • Seokhyeon Jeong · Inhee Lee · David Blaauw · Dennis Sylvester ·
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    ABSTRACT: This work presents an ultra-low-power oscillator designed for wake-up timers in compact wireless sensors. In a conventional relaxation oscillator, a capacitor periodically resets to a fixed voltage using a continuous comparator, thereby generating an output clock. The reset is triggered by a continuous comparator and thus the clock period is dependent on the delay of the continuous comparator which therefore needs to be fast compared to the period, making this approach power hungry. To avoid the power penalty of a fast continuous comparator, a constant charge subtraction scheme is proposed in this paper. As a constant amount of charge is subtracted for each cycle, rather than discharging/charging the capacitor to a fixed voltage, the clock period becomes independent of comparator delay. Therefore, the high power continuous comparator can be replaced with a coarse clocked comparator, facilitating low-power time tracking. For precise wake-up signal generation, an accurate continuous comparator is only enabled for one clock period at the end of the specified wakeup time. A wake-up timer using the proposed scheme is fabricated in a 0.18 µm CMOS process. The timer consumes 5.8 nW at room temperature with temperature stability of 45 ppm/°C (-10 °C to 90 °C) and line sensitivity of 1%/V (1.2 V to 2.2 V) .
    IEEE Journal of Solid-State Circuits 08/2015; 50(8):1-10. DOI:10.1109/JSSC.2015.2413133 · 3.01 Impact Factor
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    ABSTRACT: Indoor photovoltaic energy harvesting is a promising candidate to power millimeter (mm)-scale systems. The theoretical efficiency and electrical performance of photovoltaics under typical indoor lighting conditions are analyzed. Commercial crystalline Si and fabricated GaAs and Al0.2Ga0.8As photovoltaic cells were experimentally measured under simulated AM 1.5 solar irradiation and indoor illumination conditions using a white phosphor light-emitting diode to study the effects of input spectra and illuminance on performance. The Al0.2Ga0.8As cells demonstrated the highest performance with a power conversion efficiency of 21%, with open-circuit voltages >0.65 V under low lighting conditions. The GaAs and Al0.2Ga0.8As cells each provide a power density of nW/mm or more at 250 lx, sufficient for the perpetual operation of present-day low-power mm-scale wireless sensor nodes.
    IEEE Transactions on Electron Devices 07/2015; 62(7):2170-2175. DOI:10.1109/TED.2015.2434336 · 2.47 Impact Factor
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    ABSTRACT: A dual-slope capacitance-to-digital converter for pressure-sensing is presented and demonstrated in a complete microsystem. The design uses base capacitance subtraction with a configurable capacitor bank to narrow down input capacitance range and reduce conversion time. An energy-efficient iterative charge subtraction method is proposed, employing a current mirror that leverages the 3.6 V battery supply available in the system. We also propose dual-precision comparators to reduce comparator power while maintaining high accuracy during slope conversion, further improving energy efficiency. The converter occupies 0.105 mm$^{2}$ in 180 nm CMOS and achieves 44.2 dB SNR at 6.4 ms conversion time and 110 nW of power, corresponding to 5.3 pJ/conv-step FoM. The converter is integrated with a pressure transducer, battery, processor, power management unit, and radio to form a complete 1.4 mm$times$ 2.8 mm $times$ 1.6 mm pressure sensor system aimed at implantable devices. The multi-layer system is implemented in 180 nm CMOS. The system was tested for resolution in a pressure chamber with an external 3.6 V supply and serial communication bus, and the measured resolution of 0.77 mmHg was recorded. We also demonstrated the wireless readout of the pressure data on the stack system operating completely wirelessly using an integrated battery.
    IEEE Journal of Solid-State Circuits 07/2015; 50(7):1-11. DOI:10.1109/JSSC.2015.2435736 · 3.01 Impact Factor
  • Supreet Jeloka · Naveen Akesh · Dennis Sylvester · David Blaauw ·
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    ABSTRACT: Conventional Content Addressable Memory (BCAM and TCAM) uses specialized 10T / 16T bit cells that are significantly larger than 6T SRAM cells. We propose a new BCAM/TCAM that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the CAM as an SRAM. Using a 6T 28nm FDSOI SRAM bit cell, the 64×64 (4kb) BCAM achieves 370 MHz at 1V and consumes 0.6fJ/search/bit.
    VLSI Circuits (VLSI Circuits), 2015 Symposium on, Kyoto, Japan; 06/2015
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    ABSTRACT: This work proposes an area-efficient approach to fully exploit redundancy in reconfigurable sense amplifiers (SAs). The proposed SA can combine/invert offsets of sub-unit SAs, reducing offset by up to 3.1× at iso-area in 28nm FDSOI.
    VLSI Circuits (VLSI Circuits), 2015 Symposium on, Kyoto, Japan; 06/2015
  • Dong-Woo Jee · Dennis Sylvester · David Blaauw · Jae-Yoon Sim ·
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    ABSTRACT: This paper presents an all-digital multiplying delay-locked loop (MDLL) with a leakage-based oscillator for ultra-low-power sensor platforms. The proposed digital control of channel leakage current achieved ultra-low-power consumption in frequency generation with a fine resolution. The leakage based oscillator was modeled as an RC-based oscillator, analyzed, and the analyses were verified by simulation. The proposed oscillator was applied to the MDLL with a fast frequency relocking scheme which adaptively performs an optimal lock process according to the amount of frequency drift during the sleep state. The MDLL was implemented in 65 nm CMOS and consumed 423 nW for 3.2 MHz generation, and had an energy efficiency FoM of 0.132 W/MHz.
    IEEE Journal of Solid-State Circuits 05/2015; 50(5):1263-1274. DOI:10.1109/JSSC.2015.2403369 · 3.01 Impact Factor
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    ABSTRACT: In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study.
    IEEE Journal of Solid-State Circuits 05/2015; 50(5):1310-1323. DOI:10.1109/JSSC.2015.2408332 · 3.01 Impact Factor
  • W. Lim · I. Lee · D. Sylvester · D. Blaauw ·
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    ABSTRACT: Recent low-voltage design techniques have enabled dramatic improvements in miniaturization and lifetime of wireless sensor nodes [1-3]. These systems typically use a secondary battery to provide energy when the sensor is awake and operating; the battery is then recharged from a harvesting source when the sensor is asleep. In these systems, the key requirement is to minimize energy per operation of the sensor. This extends the number of operations on one battery charge and/or reduces the time to recharge the battery between awake cycles. This requirement has driven significant advances in energy efficiency [1-2] and standby power consumption [3].
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 03/2015; 58:146-147. DOI:10.1109/ISSCC.2015.7062968
  • K. Yang · Q. Dong · D. Blaauw · D. Sylvester ·
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    ABSTRACT: Security is a key concern in today's mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and chip-ID generators [1-4]. Recently, physically unclonable functions (PUFs) were proposed as a secure method for chip authentication in unsecure environments [5-7]. A PUF is a function that maps an input code ('challenge') to an output code ('response') in a manner that is unique for every chip. PUFs are increasingly used for IC authentication to offer protection against identity theft, cloning, and counterfeit components [2-4].
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 03/2015; 58:254-255. DOI:10.1109/ISSCC.2015.7063022
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    ABSTRACT: Capacitance sensors are widely used to measure various physical quantities, including position, pressure, and concentration of certain chemicals [1-6]. Integrating capacitive sensors into a small wireless sensor system is challenging due to their large power consumption relative to the total system power/energy budget, which can be as low as a few nW [4]. Typical capacitance-to-digital converters (CDCs) use charge sharing or charge transfer between capacitors to convert the sampled capacitance to voltage, which is then measured with an ADC [1-6]. This approach requires complex analog circuits, such as amplifiers and ADCs, increasing design complexity and often increasing power consumption. Moreover, the initial capacitance to voltage conversion essentially limits the input capacitance range because of output voltage saturation. This paper presents a fully digital CDC that is based on the observation that when a ring oscillator (RO) is powered from a charged capacitance, the number of RO cycles required to discharge the capacitance to a fixed voltage is naturally linear with the capacitance value. This observation enables a simple, fully digital conversion scheme that is inherently linear. As a result, the proposed CDC performs conversion across a very wide capacitance range from 0.7pF to over 10nF with < 0.06% linearity error. The CDC senses 11.3pF input capacitance with 35.1 pJ conversion energy and 141fJ/c-s FoM.
    IEEE Journal of Solid-State Circuits 02/2015; 2015. DOI:10.1109/ISSCC.2015.7063137 · 3.01 Impact Factor
  • S. Jeloka · R. Das · R.G. Dreslinski · T. Mudge · D. Blaauw ·
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    ABSTRACT: This paper proposes a novel 3D switch, called 'Hi-Rise', that employs high-radix switches to efficiently route data across multiple stacked layers of dies. The proposed interconnect is hierarchical and composed of two switches per silicon layer and a set of dedicated layer to layer channels. However, a hierarchical 3D switch can lead to unfair arbitration across different layers. To address this, the paper proposes a unique class-based arbitration scheme that is fully integrated into the switching fabric, and is easy to implement. It makes the 3D hierarchical switch's fairness comparable to that of a flat 2D switch with least recently granted arbitration. The 3D switch is evaluated for different radices, number of stacked layers, and different 3D integration technologies. A 64-radix, 128-bit width, 4-layer Hi-Rise evaluated in a 32nm technology has a throughput of 10.65 Tbps for uniform random traffic. Compared to a 2D design this corresponds to a 15% improvement in throughput, a 33% area reduction, a 20% latency reduction, and a 38% energy per transaction reduction.
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    ABSTRACT: A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.
    IEEE Journal of Solid-State Circuits 01/2015; 50(1):375-390. DOI:10.1109/JSSC.2014.2364036 · 3.01 Impact Factor
  • Nathaniel Pinckney · David Blaauw · Dennis Sylvester ·
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    ABSTRACT: ??????Energy-efficient near-threshold design has been proposed to increase energy efficiency across a wide range of applications. This article first provides a background motivating near-threshold and how it differs from super-threshold and subthreshold operation. Next, state-of-the-art near-threshold techniques are summarized that help overcome barriers to near-threshold adoption, namely high variation at low voltage. Last, example industrial and academic wide-voltage scaling systems are discussed.
    IEEE Solid-State Circuits Magazine 01/2015; 7(2):49-57. DOI:10.1109/MSSC.2015.2418151
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    ABSTRACT: This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.
    IEEE Journal of Solid-State Circuits 12/2014; 49(12):2800-2811. DOI:10.1109/JSSC.2014.2346788 · 3.01 Impact Factor
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    ABSTRACT: We present a 346 μm2 reference-free, asynchronous VCO-based sensor interface circuit demonstrated in 28 nm LP bulk CMOS. This design is specifically for sensor node interfaces which do not have the power or volume available for the high accuracy current sources, voltage sources, or low jitter timing references needed for traditional ADCs. By using a straightforward VCO design, it achieves wide resolution, voltage scalability, and process portability while consuming only ~1/100th the area of prior approaches and avoiding costly reference circuitry. In the design measured for this paper, resolution can be scaled from 2.8 to 11.7 bits and VDD from 500 mV to 1.0 V. The design contains a single-point calibration scheme that works across temperature, voltage, and resolution settings. Minimum power consumption is 11.7 μW at 0.6 V VDD and minimum energy per conversion step is 41.2 fJ/b at 0.6 V VDD and 9.42 bits of effective resolution.
    IEEE Journal of Solid-State Circuits 11/2014; 49(11):2462-2473. DOI:10.1109/JSSC.2014.2358589 · 3.01 Impact Factor
  • Seokhyeon Jeong · Inhee Lee · David Blaauw · Dennis Sylvester ·
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    ABSTRACT: This work presents an ultra-low power oscillator designed for wake-up timers in compact wireless sensors. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18μm CMOS, the oscillator consumes 5.8nW at room temperature with temperature stability of 45ppm/°C (-10°C to 90°C) and 1%V line sensitivity.
    Custom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the; 09/2014
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    ABSTRACT: We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 $mu$m CMOS and occupies 0.09 mm$^{{2}}$ while consuming 71 nW. After 2-point calibration, an inaccuracy of ${+} 1.5^{circ}{rm C}/-1.4^{circ}{rm C}$ is achieved across 0$^{circ}$ C to 100$^{circ}$ C. With a conversion time of 30 ms, 0.3 $^{circ}$C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.
    IEEE Journal of Solid-State Circuits 08/2014; 49(8):1682-1693. DOI:10.1109/JSSC.2014.2325574 · 3.01 Impact Factor
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    ABSTRACT: Deeply scaled CMOS circuits are increasingly susceptible to transient faults and soft errors; emerging post-CMOS devices can be more vulnerable, sometimes exhibiting erratic errors of arbitrary duration. Applying timing and supply voltage margin is wasteful and becoming ineffective, and conventional checking and sparing techniques provide only a limited error coverage against widely varying errors. We propose a confidence-driven computing (CDC) model for an adaptive protection against nondeterministic errors. The CDC model employs fine-grained temporal redundancy and confidence checking for a faster adaptation and tunable reliability. The CDC model can be extended to deeply scaled CMOS circuits that are mainly affected by transient faults and soft errors, where an early checking (EC) technique can be used to perform independent error checking for more flexibility and better performance. To evaluate the CDC model, we apply a sample-based field-programmable gate array emulation along with real-time error injection. The CDC model is shown to adapt to fluctuating error rates and enhance the system reliability by effectively trading off performance. To evaluate the EC technique at a finer time scale, we create a new event-based simulation to capture path delay distribution, error model, and their interactions. The EC technique improves the system reliability by more than four orders of magnitude when errors are of short duration. Both the CDC model and the EC technique are synthesized in a 45-nm CMOS technology for cost estimates: 1) the area overhead is as low as 12% and 2) energy overhead can be limited to 19%.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2014; 22(8):1727-1737. DOI:10.1109/TVLSI.2013.2277351 · 1.36 Impact Factor
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    ABSTRACT: Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network sizes have increased, the complexity of these techniques has grown as well, particularly in the case of multi-hop networks. In this paper, we propose an efficient QoS implementation for a single-stage, high-radix switch, which is readily scalable to 64 nodes. In addition to best effort and guaranteed throughput services, we implement a guaranteed latency traffic class with a latency bound. Our implementation allows systems significantly larger than most current multi-core chips to be implemented without the need for difficult and complex multi-hop QoS.

Publication Stats

12k Citations
221.81 Total Impact Points


  • 2002-2014
    • Concordia University–Ann Arbor
      Ann Arbor, Michigan, United States
  • 2001-2014
    • University of Michigan
      • • Division of Computer Science and Engineering
      • • Department of Electrical Engineering and Computer Science (EECS)
      Ann Arbor, Michigan, United States
  • 2012
    • Arizona State University
      Phoenix, Arizona, United States
  • 2009
    • ARM Ltd
      Cambridge, England, United Kingdom
  • 2005
    • Texas A&M University
      • Department of Electrical and Computer Engineering
      College Station, TX, United States
  • 2003-2005
    • University of Illinois, Urbana-Champaign
      Urbana, Illinois, United States
  • 2002-2003
    • The University of Arizona
      Tucson, Arizona, United States
  • 1997
    • Russian Academy of Sciences
      Moskva, Moscow, Russia
    • University of Texas at Austin
      Austin, Texas, United States