David Blaauw

Concordia University–Ann Arbor, Ann Arbor, Michigan, United States

Are you David Blaauw?

Claim your profile

Publications (432)191.7 Total impact

  • [Show abstract] [Hide abstract]
    ABSTRACT: A syringe-implantable electrocardiography (ECG) monitoring system is proposed. The noise optimization and circuit techniques in the analog front-end (AFE) enable 31 nA current consumption while a minimum energy computation approach in the digital back-end reduces digital energy consumption by 40%. The proposed SoC is fabricated in 65 nm CMOS and consumes 64 nW while successfully detecting atrial fibrillation arrhythmia and storing the irregular waveform in memory in experiments using an ECG simulator, a live sheep, and an isolated sheep heart.
    IEEE Journal of Solid-State Circuits 01/2015; 50(1):375-390. DOI:10.1109/JSSC.2014.2364036 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents a fully integrated energy harvester that maintains >35% end-to-end efficiency when harvesting from a 0.84 mm 2 solar cell in low light condition of 260 lux, converting 7 nW input power from 250 mV to 4 V. Newly proposed self-oscillating switched-capacitor (SC) DC-DC voltage doublers are cascaded to form a complete harvester, with configurable overall conversion ratio from 9× to 23×. In each voltage doubler, the oscillator is completely internalized within the SC network, eliminating clock generation and level shifting power overheads. A single doubler has >70% measured efficiency across 1 nA to 0.35 mA output current ( >10 5 range) with low idle power consumption of 170 pW. In the harvester, each doubler has independent frequency modulation to maintain its optimum conversion efficiency, enabling optimization of harvester overall conversion efficiency. A leakage-based delay element provides energy-efficient frequency control over a wide range, enabling low idle power consumption and a wide load range with optimum conversion efficiency. The harvester delivers 5 nW-5 μW output power with >40% efficiency and has an idle power consumption 3 nW, in test chip fabricated in 0.18 μm CMOS technology.
    IEEE Journal of Solid-State Circuits 12/2014; 49(12):2800-2811. DOI:10.1109/JSSC.2014.2346788 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a 346 μm2 reference-free, asynchronous VCO-based sensor interface circuit demonstrated in 28 nm LP bulk CMOS. This design is specifically for sensor node interfaces which do not have the power or volume available for the high accuracy current sources, voltage sources, or low jitter timing references needed for traditional ADCs. By using a straightforward VCO design, it achieves wide resolution, voltage scalability, and process portability while consuming only ~1/100th the area of prior approaches and avoiding costly reference circuitry. In the design measured for this paper, resolution can be scaled from 2.8 to 11.7 bits and VDD from 500 mV to 1.0 V. The design contains a single-point calibration scheme that works across temperature, voltage, and resolution settings. Minimum power consumption is 11.7 μW at 0.6 V VDD and minimum energy per conversion step is 41.2 fJ/b at 0.6 V VDD and 9.42 bits of effective resolution.
    IEEE Journal of Solid-State Circuits 11/2014; 49(11):2462-2473. DOI:10.1109/JSSC.2014.2358589 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. A conventional approach to generate these currents is to drop a temperature sensitive voltage across a resistor. Since a large resistance is required to achieve nWs of power consumption with typical voltage levels (100 s of mV to 1 V), we introduce a new sensing element that outputs only 75 mV to save both power and area. The sensor is implemented in 0.18 $mu$m CMOS and occupies 0.09 mm$^{{2}}$ while consuming 71 nW. After 2-point calibration, an inaccuracy of ${+} 1.5^{circ}{rm C}/-1.4^{circ}{rm C}$ is achieved across 0$^{circ}$ C to 100$^{circ}$ C. With a conversion time of 30 ms, 0.3 $^{circ}$C (rms) resolution is achieved. The sensor does not require any external references and consumes 2.2 nJ per conversion. The sensor is integrated into a wireless sensor node to demonstrate its operation at a system level.
    IEEE Journal of Solid-State Circuits 08/2014; 49(8):1682-1693. DOI:10.1109/JSSC.2014.2325574 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Deeply scaled CMOS circuits are increasingly susceptible to transient faults and soft errors; emerging post-CMOS devices can be more vulnerable, sometimes exhibiting erratic errors of arbitrary duration. Applying timing and supply voltage margin is wasteful and becoming ineffective, and conventional checking and sparing techniques provide only a limited error coverage against widely varying errors. We propose a confidence-driven computing (CDC) model for an adaptive protection against nondeterministic errors. The CDC model employs fine-grained temporal redundancy and confidence checking for a faster adaptation and tunable reliability. The CDC model can be extended to deeply scaled CMOS circuits that are mainly affected by transient faults and soft errors, where an early checking (EC) technique can be used to perform independent error checking for more flexibility and better performance. To evaluate the CDC model, we apply a sample-based field-programmable gate array emulation along with real-time error injection. The CDC model is shown to adapt to fluctuating error rates and enhance the system reliability by effectively trading off performance. To evaluate the EC technique at a finer time scale, we create a new event-based simulation to capture path delay distribution, error model, and their interactions. The EC technique improves the system reliability by more than four orders of magnitude when errors are of short duration. Both the CDC model and the EC technique are synthesized in a 45-nm CMOS technology for cost estimates: 1) the area overhead is as low as 12% and 2) energy overhead can be limited to 19%.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 08/2014; 22(8):1727-1737. DOI:10.1109/TVLSI.2013.2277351 · 1.14 Impact Factor
  • 06/2014; 31(3):8-20. DOI:10.1109/MDAT.2014.2314600
  • [Show abstract] [Hide abstract]
    ABSTRACT: Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network sizes have increased, the complexity of these techniques has grown as well, particularly in the case of multi-hop networks. In this paper, we propose an efficient QoS implementation for a single-stage, high-radix switch, which is readily scalable to 64 nodes. In addition to best effort and guaranteed throughput services, we implement a guaranteed latency traffic class with a latency bound. Our implementation allows systems significantly larger than most current multi-core chips to be implemented without the need for difficult and complex multi-hop QoS.
  • [Show abstract] [Hide abstract]
    ABSTRACT: An incremental zoom-in capacitance-to-digital converter (CDC) is proposed. By using a 9b SAR, the OSR can be reduced to only 32, significantly improving conversion energy. We show how the OTA in the SAR is bypassed for the CDC further reducing energy and propose a novel matrix based 512-element unit-cap structure for dynamic element matching. The CDC achieves 94.7dB SNR and 33.7μW power consumption with 175fJ/conv-step at 1.4V supply.
    2014 IEEE Symposium on VLSI Circuits; 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: We present a 2×4×4mm3 imaging system complete with optics, wireless communication, battery, power management, solar harvesting, processor and memory. The system features a 160×160 resolution CMOS image sensor with 304nW continuous in-pixel motion detection mode. System components are fabricated in five different IC layers and die-stacked for minimal form factor. Photovoltaic (PV) cells face the opposite direction of the imager for optimal illumination and generate 456nW at 10klux to enable energy autonomous system operation.
    2014 IEEE Symposium on VLSI Circuits; 06/2014
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: An ARM-based sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. The ultra-low power chip featuring an ARM Cortex-M0 processor, 3kB of SRAM, and power management unit (PMU) with energy harvesting from MFCs is designed to consume 11nW in sleep mode for perpetual sensing operation. A small-scale micro-MFC with 21.3cm 2 anode surface area was connected to the on-chip PMU to charge a thin film battery of 1mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1 sec wake-up time demonstrated the sustainability of chip-on-mud concept. During sleep mode, the system charges the 4V battery at 380nA from the micro-MFC generating 5.4µW of power, which can support up to 20mA of active mode current.
    IEEE Internaional Symposium on Circuits and Systems (ISCAS), Melbourne, Australia; 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Low power electronic circuitry, including wirelessly interconnected sensor nodes, is a transformational technology that can be applied to a broad range of applications. These low power systems still require electrical power, ideally from ambient energy sources. Ambient sources of light can provide sufficient energy for these applications. Stray sunlight is more than adequate, though it is not available in all locations. Indoor lighting may also provide a sufficient energy source, though the characteristics of the spectrum are significantly different than the solar spectrum, where irradiance is confined to a narrower window in the visible spectrum. Energy-autonomous operation in mm-scale sensors have been achieved using photovoltaics based on silicon CMOS [1,2]. Improvements in energy harvesting are necessary to increase the duty cycle of the microsystem and to facilitate wireless transceivers. Photovoltaic cells consisting of materials with larger bandgap energy, such as GaAs, provide a better match to the indoor light spectrum, reducing thermalization losses and increasing power generation. The larger voltage provided by higher bandgap materials such as GaAs can also improve the efficiency of the overall system, where higher voltages are beneficial for the battery storage system and DC-DC converter. While the cost of GaAs photovoltaics is significantly higher than for silicon, and is currently prohibitive for large area solar energy production, the small power requirements and associated size requirements for photovoltaic cells makes GaAs an affordable option. Requirements for active and standby power are 10μW and 0.5nW, respectively[1,2], where perpetual operation may be achieved using a photovoltaic cell with area on the order of 1 mm2.
    2014 72nd Annual Device Research Conference (DRC); 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: We propose a battery supervisory circuit (BSC) for wireless sensor nodes that automatically adapts to varying battery health, as reflected by its internal resistance (RBAT), and establishes a constant effective threshold voltage. Compared to a conventional fixed-threshold BSC, the new design avoids oscillation and widens the usable range of battery voltages, independent of RBAT. RBAT is measured by inducing a test current using decaps and measuring the resulting battery RC response time. When tested with a 2μAh battery and 11μA sensor system, the BSC reduces the required hysteresis from 656mV to 77mV, increasing the usable battery voltage range by 2.7×.
    2014 IEEE Symposium on VLSI Circuits; 06/2014
  • Yen-Po Chen, David Blaauw, Dennis Sylvester
    [Show abstract] [Hide abstract]
    ABSTRACT: A low power high efficiency neural signal recording amplifier with a novel multi-chopper technique is proposed and implemented in 180nm CMOS. The input referred rms noise is 1.54μV (1-500Hz) with 266nA tail current. The result corresponds to a 1.38 noise efficiency factor, which is the best reported among current state-of-the-art amplifiers.
    2014 IEEE Symposium on VLSI Circuits; 06/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents an energy-efficient feature extraction accelerator design aimed at visual navigation. The hardware-oriented algorithmic modifications such as a circular-shaped sampling region and unified description are proposed to minimize area and energy consumption while maintaining feature extraction quality. A matched-throughput accelerator employs fully-unrolled filters and single-stream descriptor enabled by algorithm-architecture co-optimization, which requires lower clock frequency for the given throughput requirement and reduces hardware cost of description processing elements. Due to the large number of FIFO blocks, a robust low-power FIFO architecture for the ultra-low voltage (ULV) regime is also proposed. This approach leverages shift-latch delay elements and balanced-leakage readout technique to achieve 62% energy savings and 37% delay reduction. We apply these techniques to a feature extraction accelerator that can process 30 fps VGA video in real time and is fabricated in 28 nm LP CMOS technology. The design consumes 2.7 mW with a clock frequency of 27 MHz at Vdd = 470 mV, providing 3.5× better energy efficiency than previous state-of-the-art while extracting features from entire image.
    IEEE Journal of Solid-State Circuits 05/2014; 49(5):1271-1284. DOI:10.1109/JSSC.2014.2309692 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: The majority of the power consumption of a high-throughput LDPC decoder is spent on memory. Unlike in a general-purpose processor, the memory access in an LDPC decoder is deterministic and the access window is short. We take advantage of the unique memory access characteristic to design a non-refresh eDRAM that holds data for the necessary access window, and further improve its access time by trading off the excess retention time. The resulting 3T eDRAM cell is designed to balance wordline coupling to reliably retain data for a fast access. We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard. Memory refresh is eliminated and random access is replaced with a simple sequential addressing. With row merging and dual-frame processing, the 1.6 mm 2 65 nm LDPC decoder chip achieves a peak throughput of 9 Gb/s at 89.5 pJ/b, of which only 21% is spent on eDRAMs. With voltage and frequency scaling, the power consumption of the LDPC decoder is reduced to 37.7 mW for a 1.5 Gb/s throughput at 35.6 pJ/b.
    IEEE Journal of Solid-State Circuits 03/2014; 49(3):783-794. DOI:10.1109/JSSC.2014.2300417 · 3.11 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Voltage scaling is widely used to improve SRAM energy efficiency [1-2], particularly in mobile systems with tight power budgets. The resulting energy benefits are limited by the minimum voltage ensuring error-free operation, Vmin, which has stagnated due to growing process variation in advanced technology nodes [3]. Error-tolerant applications and systems (e.g., multimedia) allow more aggressive voltage scaling by operating below Vmin, which is acceptable if errors due to bitcell write/read failures do not perceptibly reduce application quality (e.g., image quality). Unfortunately, in traditional SRAMs bit error rate degrades rapidly for VDD <; Vmin [4], limiting energy gains. Under a given quality target, further energy reduction is possible through application-specific methods that exploit the features of data stored in a given application [4-5]. However, these approaches are not reusable across applications, and further the energy-quality trade-off is fixed at design time, which degrades energy savings in applications with lower quality targets and in chips near typical corner
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, San Francisco, CA; 02/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Electrocardiography (ECG) is a critical source of information for a number of heart disorders. In arrhythmia studies and treatment, long-term observation is critical to determine the nature of the abnormality and its severity. However, even small body-wearable systems can impact a patient's everyday life and signals captured using such systems are prone to noise from sources such as 60Hz power and body movement. In contrast, implanted devices are less susceptible to these noise sources and, while having closer-spaced electrodes, can obtain similar quality ECG signals due to their proximity to the heart [1]. In addition, implanted devices enable continuous monitoring without affecting patient quality of life. As in other implantable systems, low power consumption is a critical factor; in this case to provide a sufficiently long operating time between wireless recharge events.
    2014 IEEE International Solid- State Circuits Conference (ISSCC); 02/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work presents an area-efficient and variation-tolerant small-signal differential sensing (VTS) scheme that modifies the conventional SA circuit to include: 1) a structure for on-the-fly, auto-zeroing offset compensation, 2) pre-amplification of bitline differential by reconfiguring the SA inverter pair as amplifiers, and 3) latching of the amplified voltage differential by returning the SA to its conventional cross-coupled configuration. The approach is demonstrated to improve SA robustness over conventional sensing at isosensing time without area overhead (Fig. 13.7.1). Conversely, sensing time can be reduced at iso-robustness and area. Measurements of a 28nm CMOS test chip show that an iso-area VTS scheme improves offset noise tolerance by -1.2σVth or sensing speed by up to 42% at iso-robustness (<;0.3% failure rate).
    2014 IEEE International Solid- State Circuits Conference (ISSCC); 02/2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: Recent advances in nW-level wireless sensor nodes have created opportunities in emerging applications such as bio-implantable telemetry, smart healthcare, and environmental monitoring [1]. At the same time, there are many circuit and system design challenges to achieving high functionality in such ultra-low-power microsystems. One of the key sensing modalities in these systems is capacitive sensing. With zero static current during signal readout, capacitive sensing is well suited to ultra-low-power microsystems and has been widely adopted in the sensing of pressure [2,3], displacement [4], and humidity [5].
    2014 IEEE International Solid- State Circuits Conference (ISSCC); 02/2014

Publication Stats

10k Citations
191.70 Total Impact Points

Institutions

  • 2002–2014
    • Concordia University–Ann Arbor
      Ann Arbor, Michigan, United States
  • 2001–2014
    • University of Michigan
      • Department of Electrical Engineering and Computer Science (EECS)
      Ann Arbor, Michigan, United States
  • 2011
    • Synopsys
      Mountain View, California, United States
  • 2009
    • ARM Ltd
      Cambridge, England, United Kingdom
  • 2005
    • Texas A&M University
      • Department of Electrical and Computer Engineering
      College Station, TX, United States
  • 2003–2005
    • University of Illinois, Urbana-Champaign
      Urbana, Illinois, United States
  • 2004
    • Sun Pharma USA
      Philadelphia, Pennsylvania, United States
  • 2002–2003
    • The University of Arizona
      Tucson, Arizona, United States
  • 1997
    • Russian Academy of Sciences
      Moskva, Moscow, Russia