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2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, Ghent, Belgium, Aug. 22-25, 2011; 01/2011
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18th IEEE International Conference on Image Processing, ICIP 2011, Brussels, Belgium, September 11-14, 2011; 01/2011
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ABSTRACT: In Computer Vision and Pattern Recognition, the object detection problem is a fundamental task, but only a few systems are thought to be realized on an embedded architecture. To this end, we propose an effective, low-latency, affordable classification architecture, especially suited for embedded platforms. In particular, we have designed a novel highly-parallelizable classification framework for an FPGA-based implementation, which is suitable for generic detection problems. The underlying model consists in a weighted sum of boosted binary classifiers, learned on a set of overlapped image patches. Each patch is described by estimating the covariance matrix of a set of features, so forming a very compact and expressive descriptor. Covariances matrices live on Riemannian Manifold, whose topology is particularly simple, so that they can be approximated in the Euclidean Vector Space in a cheap and conservative way. The hardware design has been developed in a parallel fashion and with specific architectural solutions, allowing a fast response without degrading the functional performances. We finally specialize this architecture to the challenging pedestrian detection problem, defining state-of-the art results on the standard INRIA pedestrian benchmark dataset.
Database and Expert Systems Applications, DEXA, International Workshops, Bilbao, Spain, August 30 - September 3, 2010; 01/2010
