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ABSTRACT: Spectrum sensing is a key enabler of cognitive radio but generally suffers from what is called a signal-to-noise ratio (SNR) wall, i.e., a minimum SNR below which it is impossible to reliably detect a signal. For energy detection, which has the advantage of not requiring knowledge of the signal, the SNR wall is caused by uncertainty in the noise level. Cross-correlation has been suggested as a possible means to obtain higher sensitivity but has received little attention in the context of noise uncertainty. The idea of cross-correlation is to have two receive paths, where each path independently processes the signal before they are combined, such that the noise added to the input signal at the individual paths is largely uncorrelated. In this paper, we mathematically quantify the SNR wall for cross-correlation, showing that it linearly scales with the amount of noise correlation. This lower noise correlation results in higher sensitivity, which is significantly better than that for autocorrelation. Equations that can be used to estimate the benefit over autocorrelation and the measurement time for a required probability of detection and false alarm are derived.
IEEE Transactions on Vehicular Technology 11/2011; · 1.92 Impact Factor
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ABSTRACT: In this paper, we explore the robustness of frequency references based on the electron mobility in a MOS transistor by implementing them with both thin-oxide and thick-oxide MOS transistors in a 0.16-μm CMOS process, and by testing samples packaged in both ceramic and plastic packages. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for applications requiring fully integrated solutions, such as Wireless Sensor Networks. Over the temperature range from -55°C to 125°C, its frequency spread is less than ±1% (3σ) after a one-point trim. Fabricated in a baseline 0.16-μm CMOS process, the 50 kHz frequency reference occupies 0.06 mm<sup>2</sup> and, at room temperature, its consumption with a 1.2-V supply is less than 17 μW.
ESSCIRC (ESSCIRC), 2011 Proceedings of the; 10/2011
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ABSTRACT: A temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55°C to 125°C , the frequency spread of the complete reference is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm<sup>2</sup> and draws 42.6 μA from a 1.2-V supply at room temperature.
IEEE Journal of Solid-State Circuits 08/2011; · 3.23 Impact Factor
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ABSTRACT: This work proposes a direct conversion transmitter architecture intended for cognitive radio applications. The architecture is based on the poly-phase multipath technique, which has been shown to cancel out many of the harmonics, sidebands and nonlinearity contributions of a power up converter using a large number of signal paths. This work proposes a design only using 8 paths which is able to achieve <;-40dBc harmonic suppression for all harmonics, including the dominant 7<sup>th</sup> and 9<sup>th</sup> harmonic. This is done with a combination of duty cycle control of the Local Oscillator (LO) waveform and tunable filtering with only a first order roll-off.
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on; 06/2011
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ABSTRACT: Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on; 06/2011
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ABSTRACT: A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P<sub>1dB</sub>=2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).
IEEE Journal of Solid-State Circuits 06/2011; · 3.23 Impact Factor
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ABSTRACT: Phased-array receivers provide two major benefits over single-antenna receivers. Their signal-to-noise ratio (SNR) doubles for each doubling in the number of elements, resulting in extended range. Secondly, interferers can be rejected in the spatial domain for increased link robustness. These arrays can be implemented by phase shifting and summing the signals from antenna elements with uniform spacing. For accurate interference rejection, a phase shifter with uniform phase steps and constant amplitude is desired. Several types of continuous-time phase shifters have been published, e.g. using injection locking, phase selection and vector modulation. This paper proposes a phased-array receiver architecture with a discrete-time vector modulator that takes advantage of the high linearity and good matching of switched-capacitor circuits, which are highly compatible with advanced CMOS. A simple charge redistribution circuit is presented that performs a rational approximation of the sine and cosine needed for the vector modulator weights.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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ABSTRACT: An NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of (3σ ) and a trimmed inaccuracy of (3σ) over the temperature range from to 125 . This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 from a 1.2-V supply and occupies an area of 0.1 mm<sup>2</sup>
IEEE Journal of Solid-State Circuits 01/2011; · 3.23 Impact Factor
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ABSTRACT: A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis.
Circuits and Systems I: Regular Papers, IEEE Transactions on 11/2010; · 1.97 Impact Factor
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ABSTRACT: For the first time, a temperature-compensated CMOS frequency reference based on the electron mobility in a MOS transistor is presented. Over the temperature range from -55°C to 125 °C, its frequency spread is less than ±0.5% after a two-point trim and less than ±2.7% after a one-point trim. These results make it suitable for use in Wireless Sensor Network nodes. Fabricated in a baseline 65-nm CMOS process, the 150 kHz frequency reference occupies 0.2 mm<sup>2</sup> and draws 42.6 μA from a 1.2-V supply at room temperature.
ESSCIRC, 2010 Proceedings of the; 10/2010
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ABSTRACT: A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation.
IEEE Journal of Solid-State Circuits 10/2010; · 3.23 Impact Factor
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ABSTRACT: The design of a duty-cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately accurate low-power high-frequency synthesizer suitable for use in nodes for wireless sensor networks (WSN). Thanks to a dual loop configuration, the PLL's total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65 nm CMOS technology, the DCPLL circuit occupies 0.19 x 0.15 mm<sup>2</sup> and draws 200 μA from a 1.3 V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.
IEEE Journal of Solid-State Circuits 08/2010; · 3.23 Impact Factor
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ABSTRACT: A divider-less PLL exploits a phase detector that directly samples the VCO with a reference clock. No VCO sampling buffer is used while dummy samplers keep the VCO spur <;-56dBc. A modified inverter with low short-circuit current acts as a power efficient reference clock buffer. The 2.2 GHz PLL in 0.18 μm CMOS achieves -125dBc/Hz in-band phase noise with only 700 μW loop-components power.
VLSI Circuits (VLSIC), 2010 IEEE Symposium on; 07/2010
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ABSTRACT: This paper shows that the group delay of a delay circuit does not give sufficient information to predict the delay vs. frequency. A new criterion (f<sub>φ=0</sub>) is proposed that characterizes the delay variations over a specified frequency range. The mathematical derivation of f<sub>φ=0</sub> for a single delay block and a cascade of delay blocks is shown. As examples the criterion is applied to the design of an RC and LC delay block. Delay predictions based on f<sub>φ=0</sub> compared with simulation results, showing reasonable agreement.
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on; 07/2010
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ABSTRACT: A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between +38 and +49 dBm and the IIP3 between -14 dBm and -9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.
IEEE Journal of Solid-State Circuits 06/2010; · 3.23 Impact Factor
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ABSTRACT: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115Ã225 μm<sup>2</sup>. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.
IEEE Journal of Solid-State Circuits 06/2010; · 3.23 Impact Factor
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ABSTRACT: Spectrum sensing for cognitive radio requires a high linearity to handle strong signals, and at the same time a low noise figure (NF) to enable detection of much weaker signals. Often there is a trade-off between linearity and noise: improving one of them degrades the other. Cross-correlation can break this trade-off by reducing noise at the cost of measurement time. An existing RF front-end in CMOS-technology with IIP3=+11dBm and NF<6.5dB is duplicated and attenuators are put in front to increase linearity (IIP3=+24dBm). The attenuation degrades NF, but by using cross-correlation of the outputs of the two frontends, the NF is reduced to below 4dB. In total this results in a spurious-free dynamic range (SFDR) of 89dB in 1MHz resolution bandwidth (RBW).
New Frontiers in Dynamic Spectrum, 2010 IEEE Symposium on; 05/2010
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ABSTRACT: A 65 nm CMOS 2.4 GHz wake-up receiver operating with low-accuracy frequency references has been realized. Robustness to frequency inaccuracy is achieved by employing non-coherent energy detection, broadband-IF heterodyne architecture and impulse-radio modulation. The radio dissipates 415 ¿W at 500 kb/s and achieves a sensitivity of -82 dBm with an energy efficiency of 830 pJ/bit.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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ABSTRACT: A temperature sensor utilizing NPN transistors has been realized in a 65 nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5°C (3σ) and a trimmed inaccuracy of ±0.2°C (3σ)from -70°C to 125°C The sensor draws 8.3 μA from a 1.2 V supply and occupies an area of 0.1 mm<sup>2</sup>.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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ABSTRACT: A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
