[show abstract][hide abstract] ABSTRACT: The complexity of droplet hydrodynamics on a digital microfluidic (DMF) system eventually weakens its potential for application in large-scale chemical/biological micro-reactors. We describe here an intelligent DMF technology to address that intricacy. A wide variety of control-engaged droplet manageability is proposed and demonstrated through the operation of our modular DMF prototype, which comprises: (i) rigid profiling ability of different droplet’s hydrodynamics under a real-time trajectory track of dropletderived capacitance, permitting accurate and autonomous multi-droplet positioning without visual setup and heavy image signal processing; (ii) fuzzy-enhanced controllability saving up to 21% charging time when compared with the classical approach, enhancing the throughput, fidelity and lifetime of the DMF chip, while identifying and renouncing those weakened electrodes deteriorated over time, and (iii) expert manipulability of multi-droplet routings under countermeasure decisions in real time, preventing dropletto-droplet or task-to-task interference. Altogether, this work exhibits the first modular DMF system with built-in electronic-control software-defined intelligence to enhance the fidelity and reliability of each droplet operation, allowing future manufacturability of a wide range of life science analyses and combinatorial chemical screening applications.
[show abstract][hide abstract] ABSTRACT: LATE-PCR is an advanced form of non-symmetric PCR that efficiently generates single-stranded DNA which can readily be characterized at the end of amplification by hybridization to low-temperature fluorescent probes. We demonstrate here for the first time that monoplex and duplex LATE-PCR amplification and probe target hybridization can be carried out in double layered PDMS microfluidics chips containing dried reagents. Addition of a set of reagents during dry down overcomes the common problem of single-stranded oligonucleotide binding to PDMS. These proof-of-principle results open the way to construction of inexpensive point-of-care devices that take full advantage of the analytical power of assays built using LATE-PCR and low-temperature probes.
[show abstract][hide abstract] ABSTRACT: Most biopotential readout front-ends rely on the g m- C lowpass filter (LPF) for forefront signal conditioning. A small g m realizes a large time constant ( τ = C / g m) suitable for ultra-low-cutoff filtering, saving both power and area. Yet, the noise and linearity can be compromised, given that each g m cell can involve one or several noisy and nonlinear V- I conversions originated from the active devices. This paper proposes the subthreshold-source-follower (SSF) Biquad as a prospective alternative. It features: 1) a very small number of active devices reducing the noise and nonlinearity footsteps; 2) No explicit feedback in differential implementation, and 3) extension of filter order by cascading. This paper presents an in-depth treatment of SSF Biquad in the nW-power regime, analyzing its power and area tradeoffs with gain, linearity and noise. A gain-compensation (GC) scheme addressing the gain-loss problem of NMOS-based SSF Biquad due to the body effect is also proposed. Two 100-Hz 4th-order Butterworth LPFs using the SSF Biquads with and without GC were fabricated in 0.35- μm CMOS. Measurement results show that the non-GC (GC) LPF can achieve a DC gain of -3.7 dB (0 dB), an input-referred noise of 36 μV rms (29 μV rms ), a HD3@60 Hz of -55.2 dB ( - 60.7 dB) and a die size of 0.11 mm(2) (0.08 mm(2)). Both LPFs draw 15 nW at 3 V. The achieved figure-of-merits (FoMs) are favorably comparable with the state-of-the-art.
IEEE Transactions on Biomedical Circuits and Systems 10/2013; 7(5):690-702. · 2.74 Impact Factor
[show abstract][hide abstract] ABSTRACT: Portable/Implantable biomedical applications usually exhibit stringent power budgets for prolonging battery life time, but loose operating frequency requirements due to small bio-signal bandwidths, typically below a few kHz. The use of sub-threshold digital circuits is ideal in such scenario to achieve optimized power/speed tradeoffs. This paper discusses the design of a sub-threshold standard cell library using a standard 0.18-µm CMOS technology. A complete library of 56 standard cells is designed and the methodology is ensured through schematic design, transistor width scaling and layout design, as well as timing, power and functionality characterization. Performance comparison between our sub-threshold standard cell library and a commercial standard cell library using a 5-stage ring oscillator and an ECG designated FIR filter is performed. Simulation results show that our library achieves a total power saving of 95.62% and a leakage power reduction of 97.54% when compared with the same design implemented by the commercial standard cell library (SCL).
Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference 07/2013; 2013:1454-1457.
[show abstract][hide abstract] ABSTRACT: The complexity of droplet hydrodynamics on a digital microfluidic (DMF) system eventually weakens its potential for application in large-scale chemical/biological micro-reactors. We describe here an intelligent DMF technology to address that intricacy. A wide variety of control-engaged droplet manageability is proposed and demonstrated through the operation of our modular DMF prototype, which comprises: (i) rigid profiling ability of different droplet's hydrodynamics under a real-time trajectory track of droplet-derived capacitance, permitting accurate and autonomous multi-droplet positioning without visual setup and heavy image signal processing; (ii) fuzzy-enhanced controllability saving up to 21% charging time when compared with the classical approach, enhancing the throughput, fidelity and lifetime of the DMF chip, while identifying and renouncing those weakened electrodes deteriorated over time, and (iii) expert manipulability of multi-droplet routings under countermeasure decisions in real time, preventing droplet-to-droplet or task-to-task interference. Altogether, this work exhibits the first modular DMF system with built-in electronic-control software-defined intelligence to enhance the fidelity and reliability of each droplet operation, allowing future manufacturability of a wide range of life science analyses and combinatorial chemical screening applications.
[show abstract][hide abstract] ABSTRACT: High-color-depth LCD drivers require nF-range capacitors as the charge reservoirs to handle the glitch energy during the conversion of the DAC . The reference buffers based on multi-stage amplifiers can enhance the precision under low-voltage supplies, but are exposed to instability when loaded by such large capacitive loads (CL). Frequency compensation via damping-factor control  is capable of extending the CL-drivability up to 1nF, however, at the cost of penalizing the power (426μW) and area (0.14mm2). Although recent works [3–4] have enhanced gain-bandwidth product (GBW) and slew rate (SR) showing better FOMS (=GBW·CL/Power) and FOML (=SR·CL/Power), the CL-drivability has not been improved (i.e., 0.8nF in  and 0.15nF in ). This paper describes a three-stage amplifier managed to afford particularly large and wide range of CL (1 to 15nF) with optimized power (144μW) and die size (0.016mm2), being very suitable for compact LCD drivers  with different resolution targets. The design barriers are methodically surmounted via local feedback loop (LFL) analysis expanded from , which is an insightful control-centric method. Measured at 15nF CL, the attained FOMS (FOML) is >4.48× (>2.55×) beyond that of the state-of-the-art (Fig. 21.6.1).
[show abstract][hide abstract] ABSTRACT: Wireless and semiconductor industries have recently discussed their vision of fully autonomous and seamless wireless connectivity by combining advanced nanoscale CMOS technologies with innovative hybrid-domain circuits and systems solutions. One goal inside this broad vision is to develop a smart mobile companion device with high performance, adaptive connectivity, and high power efficiency. High performance is the essential ingredient to coping with the ever-increasing add-on functionalities in small handheld devices, integrating cellular, WiFi, Bluetooth, Global Positioning System and mobile TV. All of these generate many opportunities for furthering the horizons of radio frequency integrated circuits (RFICs) in the years to come.
[show abstract][hide abstract] ABSTRACT: This paper describes an ultra-low-power filtering technique for biomedical applications designated as T-wave sensing in heart-activities detection systems. The topology is based on a source-follower-based Biquad operating in the sub-threshold region. With the intrinsic advantages of simplicity and high linearity of the source-follower, ultra-low-cutoff filtering can be achieved, simultaneously with ultra low power and good linearity. An 8(th)-order 2.4-Hz lowpass filter design example optimized in a 0.35-μm CMOS process was designed achieving over 85-dB dynamic range, 74-dB stopband attenuation and consuming only 0.36 nW at a 3-V supply.
Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference 08/2011; 2011:1859-62.
[show abstract][hide abstract] ABSTRACT: This paper introduces a novel switch approach for redundant capacitive DACs of a 2b-per-cycle SAR ADC. By using the proposed multi-merged switching algorithm, the conventional trial-and-error search procedure is prevented, which leads to significant switching energy and DAC settling time reductions. The conversion power and speed analysis are presented, which is also verified in behavior simulations of a 6- bit 2b/cycle SAR ADC. The simulation results show that the proposed method can achieve about 37% power saving as compared to the conventional one.
[show abstract][hide abstract] ABSTRACT: ,. Converting more than one bit per cycle in SA schemes requires using multiple reference voltages that scale along the conversion cycle. Since this need leads to complex and multiple capacitor-based DACs , this design uses a Kelvin divider and an effective switch-selection network. Moreover, dynamic bit registers and synchronous successive approximation operation avoid the possible speed bottleneck established by a conventional SAR logic. Figure 10.5.1 shows the block diagram of the proposed architecture. The shift registers control 170 switches to provide two differential reference voltages, VrH and VrL. Two sampling front-ends generate the difference between input and references. The differential signals serve a 3-level interpolation network with three fast comparators. An on-chip foreground offset calibration circuit minimizes the offset of the comparators. The scheme adjusts the comparator offset with digitally controlled MOS-capacitance located at the output of the comparator. The use of interpolation reduces the number of switches and shift registers, and results in diminishing consumed power and area. Figure 10.5.2 shows the schematic of the sampling front end. Capacitors CS sample the input signal during the sampling phase, ΦS, and hold it for the entire conversion period. The reference voltages at the left terminal of CS shift the differential voltages Vin at the comparator input. The use of a resistive DAC enables a very fast settling with a relatively small dynamic and reasonable power, since it is required to charge only the parasitic capacitances including the parasitics of switches, input capacitance of the comparator and parasitics of the CS, but not the CS itself due to the high-impedance node at the comparator input. Clock feed-through occurring when sampling the input signal is a key limit to the overall accuracy. Bootstrapping the sampling switch, driven with an almost constant VGS, minimizes the clock feed-through. However, the rising edge of the bootstrapped clock phase depends on Vin. This determines a second-order signal-dependent clock feed-through term that is alleviated by the cross-connected capacitance CC. The value of CC matches the parasitic Cgd of MSW.
[show abstract][hide abstract] ABSTRACT: In this paper, a novel structure of dual-VCO-based quantizer is introduced to significantly improve the VCO linearity. Compared with the precedent methods, the proposed structure can accomplish the linearity without sacrificing the intrinsic DEM function of the VCO-based quantizer, which greatly simplifies the structure of the circuit implementation. Moreover, a passive adder is introduced in this paper, instead normal active adder; the power consumption can be optimized. Besides, due to the dual-VCO structure, the dynamic range of the modulator can be greatly enlarged. A first order continuous time (CT) sigma-delta (1:11) modulator with the proposal quantizer is designed and simulated in 65 nm CMOS process. The performance of the modulator can reach 83.7/83 dB SNRlSNDR with tOMHz bandwidth and tV supply voltage.
[show abstract][hide abstract] ABSTRACT: Amethod to compensate the Excess Loop Delay (ELD) in CT I:.A modulators using Gm-C loop filter is presented. The proposed circuit architecture uses a resistor in series with the integration capacitor to obtain a feed-forward adder in the Gm-C integrator. The proposed ELD compensation is based on the Proportional Integrating (PI) -element method for low power dissipation and simple implementation, and it is verified through the design of a 2nd order CT I:.A modulator which uses a Gm-C integrator as the 2nd stage of the loop filter. To further demonstrate the efficiency of the technique a Non-Return-to Zero (NRZ) feedback is utilized due to its larger sensitivity to ELD. Simulation results show that a 68.9dB SNDR can be achieved with an ELD close to half clock period, while the system will be unstable without compensation for such an amount of the loop delay. These results confirm the effectiveness ofthe proposed ELD compensation method in Gm-C filter based CT I:.A modulators.
[show abstract][hide abstract] ABSTRACT: This paper reports a 7-bit 300-MS/s subranging ADC fabricated in standard 65nm CMOS, which utilizes embedded reference and gain loss error calibration techniques. A shared passive capacitive DAC array performs the input sampling in quantization mode and reference generation in calibration mode, providing a linear, accurate and compact calibration implementation. As a consequence of the developed calibration techniques, uniform-sized dynamic comparators are employed to reduce the process-mismatch variation and nonlinearity error, when compared with the conventional structures. The ADC achieves peak SNDR of 40.5dB at 300MS/s and 39dB at 400MS/s, with ERBW of 300MHz and 350MHz, respectively. The power consumption is 2.3mW only from 1.2-V supply at 300MS/s.
Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011; 01/2011
[show abstract][hide abstract] ABSTRACT: Noise shaping can aid ADC architectures to achieve high resolution. A new technique to increase ADC resolution is presented in this paper. It is based on Nyquist-rate ADC architectures and uses delayed analog quantization error to implement noise shaping function. The new technique is implemented using two-step and SAR ADC respectively. When the noise shaping order is one and the Over-Sampling Rate (OSR) is only 8, the system based on 5-bit two-step ADC can achieve the SNDR of 62.5-dB, while the SNDR of the system based on 6-bit SAR ADC can obtain 59.6-dB. Actually, this new technique consumes tiny amount of extra power. Although the speed of the system is decreased slightly because of the small OSR, as the resolution is increased significantly. As a result, the Figure of Merit (FOM) of the overall ADC can be improved.
[show abstract][hide abstract] ABSTRACT: A novel low-power EEG readout front-end featuring a current-mode instrumentation amplifier (CMIA) followed by a 4<sup>th</sup>-order gain-compensated source-follower-based lowpass filter (LPF) is proposed. The CMIA is of current-conveyor topology and is chopper-stabilized to improve the common-mode noise rejection and suppress the dc-offset and 1/f noise. The typical gain-loss problem of source-follower-based LPF is alleviated by adopting a gain-compensation technique. Optimized in 0.35-μm CMOS, the achieved CMRR is >100 dB from 0.01 to 16 Hz, and >90 dB up to 40 Hz. With the chopper stabilization, the noise voltage density is 248 nV√Hz at 0.01 Hz and 197 nV√Hz at 100 Hz. The power consumption is 28 μW at 3 V.
Microelectronics and Electronics (PrimeAsia), 2010 Asia Pacific Conference on Postgraduate Research in; 10/2010