[show abstract][hide abstract] ABSTRACT: Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.
Journal of Electrical and Computer Engineering. 01/2012; 2012.
[show abstract][hide abstract] ABSTRACT: We consider the problem of reducing active mode leakage power by modifying the post-synthesis netlists of combi- national logic blocks. The stacking effect is used to reduce leakage power, but instead of a separate signal one of the inputs to the gate itself is used. The approach is studied on multiplier blocks. It is found that a significant number of nets have high probabilities of being constant at 0 or 1. In specific applications such as those having high peak to average ratio, like audio and other signal processing applications, this effect is more pronounced. We show how these signals can be used to put gates to sleep, thus saving significant leakage power. I. INTRODUCTION
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India; 01/2011
[show abstract][hide abstract] ABSTRACT: The H.264 encoded video is highly sensitive to loss of motion vectors during transmission. Several statistical techniques are proposed for recovering such lost motion vectors. These use only the motion vectors that belong to the macroblocks that are horizontally or vertically adjacent to the lost macroblock, to recover the latter. Intuitively this is one of the main reasons behind why these techniques yield inferior solutions in scenarios where there is a non-linear motion. This paper proposes B-Spline based statistical techniques that comprehensively address the motion vector recovery problem in the presence of different types of motions that include slow, fast/sudden, continuous and non-linear movements. Testing the proposed algorithms with different benchmark video sequences shows an average improvement of up to 2 dB in the Peak Signal to Noise Ratio of some of the recovered videos, over existing techniques. A 2 dB improvement in PSNR is very significant from an application point of view.
IEEE Transactions on Broadcasting 01/2011; · 2.09 Impact Factor
[show abstract][hide abstract] ABSTRACT: Error concealment in video communication is becoming increasingly important because of the growing interest in video delivery over unreliable channels such as wireless networks and the Internet. A subclass of this error concealment in video communication is known as motion vector recovery (MVR). MVR techniques try to retrieve the lost motion information in the compressed video streams based on the available information in the locality (both spatial and temporal) of the lost data. The activities and practice in the area of MVR-based error concealment during the last two decades has been mainly elaborated here. A performance comparison of the prominent MVR techniques has also been presented.
[show abstract][hide abstract] ABSTRACT: This work presents a hardware implementation of an FIR filter that is self-adaptive; that responds to arbitrary frequency response landscapes; that has built-in coefficient error tolerance capabilities; and that has a minimal adaptation latency. This hardware design is based on a heuristic genetic algorithm. Experimental results show that the proposed design is more efficient than non-evolutionary designs even for arbitrary response filters. As a byproduct, the paper also presents a novel flow for the complete hardware design of what is termed as an Evolutionary System on Chip (ESoC). With the inclusion of an evolutionary process, the ESoC is a new paradigm in modern System on Chip (SoC) designs. The ESoC methodology could be a very useful structured FPGA/ASIC implementation alternative in many practical applications of FIR filters.
[show abstract][hide abstract] ABSTRACT: This study proposes a novel motion vector recovery (MVR) algorithm for the H.264 video coding standard, which takes into account the change in the motion vectors (MVs) in different directions. Existing algorithms for MVR are confined to use the horizontal or vertical directions to recover the lost MVs. However, in the presence of non-linear movements or a fast/sudden motion of any object in a scene of the given input video, the MVs recovered by these algorithms turn out to be inaccurate. The proposed directional interpolation-based technique can interpolate the MVs in any direction based on the tendency of motion around the lost macro block, thus making it suitable to handle non-linear or fast motions. Testing the proposed technique with different benchmark video sequences shows an average improvement 1-2-dB in the peak signal-to-noise ratio of the recovered video over existing techniques.
IET Image Processing 05/2010; · 0.90 Impact Factor
[show abstract][hide abstract] ABSTRACT: In a highly dynamic semiconductor manufacturing technology, the migration to the next process technology node tries to create a smaller-faster-cheaper chip. To achieve this, the integrated circuit (IC) designs are becoming more complex and new manufacturing materials/processes are introduced. Additionally, demands for sustainable yield and shorter time to volume production have to be met as they govern the profitability of the semiconductor industry. As a result, rapid yield improvement techniques are crucial to overcome huge yield losses. Any yield improvement technique typically involves detecting the yield loss (testing) and identifying its root cause (diagnosis). This paper presents a survey of the existing research work reported in the literature for test and diagnostics of nanometer chips and presents interesting open issues.
[show abstract][hide abstract] ABSTRACT: The usage of more advanced, less mature processes during manufacturing of semiconductor devices has increased the need for performing unconventional types of testing, like temperature-testing, in order to maintain the same high quality levels. However, performing temperature-testing is costly. This paper proposes a viable low-cost alternative to temperature testing that quantifies the impact of temperature variations on the test quality and also determines optimal test conditions. The test flow proposed is empirically validated on an industrial-standard die. The results obtained show that majority of the defects that were originally detected by temperature-testing are also detected by the proposed test flow, thereby reducing the dependence on temperature testing to achieve zero-defect quality. Details of an interesting defect behavior at cold test conditions is also presented.
VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010; 01/2010
[show abstract][hide abstract] ABSTRACT: Volume Yield Diagnostics (VYD) is crucial to diagnose critical systematic yield issues from the reports obtained by testing thousands of chips. This paper presents an efficient clustering technique for VYD that has been shown to work successfully both in the simulation environment as well as on real industrial failure data.
VLSI Design, 2009 22nd International Conference on; 02/2009
[show abstract][hide abstract] ABSTRACT: With the emergence of complex high-performance microprocessors, functional test generation has become a crucial design step. Constraint-based test generation is a well-studied directed behavioral level functional test generation paradigm. The paradigm involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. However, automatic extraction of constraints from a given behavioral hardware design language (HDL) model remained a challenging open problem. This paper proposes an approach for automatic extraction of word-level model constraints from the behavioral verilog HDL description. The scenarios to be tested are also expressed as constraints. The model and the scenario constraints are solved together using an integer solver to arrive at the necessary functional test. The effectiveness of the approach is demonstrated by automatically generating the constraint models for: 1) an exclusive-shared-invalid multiprocessor cache coherency model and 2) the 16-bit DLX-architecture, from their respective Verilog-based behavioral models. Experimental results that generate test vectors for high level scenarios like pipeline hazards, cache miss, etc., spanning over multiple time-frames are presented.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 05/2008; · 1.22 Impact Factor
[show abstract][hide abstract] ABSTRACT: In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a power-managed scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.
Test Conference, 2007. ITC 2007. IEEE International; 11/2007
[show abstract][hide abstract] ABSTRACT: Process variation is an increasingly dominant phenomenon affecting both power and performance in sub-100 nm technologies. Cost considerations often do not permit over-designing the power supply infrastructure for test mode, considering the worst-case scenario. Test application must not over-exercise the power supply grids, lest the tests will damage the device or lead to false test failures. The problem of debugging a delay test failure can therefore be highly complex. We argue that false delay test failures can be avoided by generating "safe" patterns that are tolerant to on-chip variations. A statistical framework for power-safe pattern generation is proposed, which uses process variation information, power grid topology and regional constraints on switching activity. Experimental results are provided on benchmark circuits to demonstrate the effectiveness of the framework.
Test Conference, 2007. ITC 2007. IEEE International; 11/2007
[show abstract][hide abstract] ABSTRACT: By generating safe patterns - those that tolerate on-chip variations - this framework avoids false delay test failures. It uses power grid information and regional constraints on switching activity to minimize peak power and optimize the pattern set. Experimental results on benchmark circuits demonstrate the framework's effectiveness.
IEEE Design and Test of Computers 08/2007; 24(4):374-384. · 1.62 Impact Factor
[show abstract][hide abstract] ABSTRACT: With increasing use of low cost wire-bond packages for mobile devices, excessive dynamic IR-drop may cause tests to fail on the tester. Identifying and debugging such scan test failures is a very complex and effort-intensive process. A better solution is to generate correct-by-construction "power-safe" patterns. Moreover, with glitch power contributing to a significant component of dynamic power, pattern generation needs to be timing-aware to minimize glitching. In this paper, we propose a timing-based, power and layout-aware pattern generation technique that minimizes both global and localized switching activity. Techniques are also proposed for power-profiling and optimizing an initial pattern set to obtain a power-safe pattern set, with the addition of minimal patterns. The proposed technique also comprehends irregular power grid topologies for constraints on localized switching activity. Experiments on ISCAS benchmark circuits reveal the effectiveness of the proposed scheme
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07; 05/2007
[show abstract][hide abstract] ABSTRACT: A hierarchical or "divide-and-conquer" scan test methodology enables us to partition a large SoC into several partitions and perform design-for-testability (DFT) functions such as scan insertion, pattern generation, and pattern validation separately on individual partitions. Since the effort for DFT related tasks grows super-linearly with gate count, partitioning reduces the effort for DFT tasks. Further, test application can be divided into k + 1 modes, where k modes correspond to independent testing of the partitions and the (k + 1)<sup>th</sup> mode corresponds to a "residual" (or daisy) mode where faults that are not covered by the individual modes are considered. In reality, however, the daisy mode can be a killer and wipe out the benefits of divide-and-conquer testing. This is especially true for partitions that do not have test wrappers. In this paper, we take up the challenge of reducing the overhead of daisy mode in divide-and-conquer testing. By a careful analysis of the interactions between partitions, additional test modes are introduced to increase the coverage of glue logic, at the same time making sure that the number of scan cells involved in these "intermediate daisy modes" are minimal. We refer to this version of hierarchical scan testing as "quiet and optimized divide-and-conquer scan". Experimental results reveal that the proposed technique reduces the test time overhead of the conventional daisy mode by about 20times. In addition, the technique drastically reduces the switching activity in the daisy modes and hence reduces the test power
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on; 02/2007
[show abstract][hide abstract] ABSTRACT: The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The power virus problem involves finding input vectors that cause maximum dynamic power dissipation (maximum toggles) in circuits. In this paper, an approach for power virus generation for both combinational and sequential circuits is presented. The basic intuition behind the approach is to use the 0- and 1- controllability measures of the gate outputs in the circuit to guide the D-algorithm. The proposed technique was employed on the ISCAS'85 and ISCAS'89 circuits. The results of the above show a significant increase in power dissipation when compared to the best known existing techniques reported in the literature
20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India; 01/2007