Tanay Karnik

Publications (22)5.39 Total impact

• Article: Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.

  Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
  IET Computers & Digital Techniques. 01/2011; 5:205-212.
• Article: All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.

  Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De
  IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2017-2025.
• Conference Proceeding: 3DICs for tera-scale computing: a case study.

  Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
  Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011; 01/2011
• Article: Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.

  Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang
  J. Solid-State Circuits. 01/2010; 45:751-758.
• Conference Proceeding: Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.

  Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De
  IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
• Conference Proceeding: Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.

  Bibiche M. Geuskens, Muhammad M. Khellah, Jaydeep Kulkarni, Tanay Karnik, Vivek De
  IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
• Conference Proceeding: Resilient microprocessor design for high performance & energy efficiency.

  Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
  Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010; 01/2010
• Conference Proceeding: A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.

  James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De
  IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010
• Conference Proceeding: PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.

  Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah
  IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010
• Conference Proceeding: Resilient design in scaled CMOS for energy efficiency.

  James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
  Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010; 01/2010
• Source

  Available from: Shih-Lien Lu

  Article: Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance

  Keith A Bowman, James W Tschanz, Nam Sung Kim, Janice C Lee, Chris B Wilkerson, Shih-Lien L Lu, Tanay Karnik, Vivek K De
  [show abstract] [hide abstract]
  ABSTRACT: A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection se-quential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly com-plex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in man-aging metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%–32% throughput gain at equal V CC or at least 17% V CC reduction at equal throughput, corresponding to 31%–37% total power reduction.
  IEEE Journal of Solid-State Circuits 01/2009; 44. · 3.23 Impact Factor
• Article: SRAM dynamic stability estimation using MPFP and its applications.

  DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De
  Microelectronics Journal. 01/2009; 40:1523-1530.
• Article: Integrated on-chip inductors using magnetic material (invited)

  Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik, Shekhar Borkar, Roy Hallstein, Tony Dambrauskas, Charles Hill, Clark Linde, Wojciech Worwag, Robert Baresel, Sriram Muthukumar
  [show abstract] [hide abstract]
  ABSTRACT: On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μH/mm2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability (>250 °C), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω, and quality factors up to 8 at frequencies as low as 40 MHz.
  Journal of Applied Physics 03/2008; 103(7):07E927-07E927-6. · 2.17 Impact Factor
• Conference Proceeding: Analytical Model for the Propagation Delay of Through Silicon Vias.

  DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De
  9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA; 01/2008
• Article: Accurate Estimation of SRAM Dynamic Stability.

  D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De
  IEEE Trans. VLSI Syst. 01/2008; 16:1639-1647.
• Conference Proceeding: Low Voltage Buffered Bandgap Reference.

  Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik
  8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA; 01/2007
• Conference Proceeding: High-frequency DC-DC conversion : fact or fiction.

  Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner
  International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
• Article: Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.

  Tanay Karnik, Peter Hazucha, Jagdish Patel
  IEEE Trans. Dependable Sec. Comput. 01/2004; 1:128-143.
• Conference Proceeding: Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.

  Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De
  Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004; 01/2004
• Conference Proceeding: Sub-90nm technologies: challenges and opportunities for CAD.

  Tanay Karnik, Shekhar Borkar, Vivek De
  Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002; 01/2002