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IET Computers & Digital Techniques. 01/2011; 5:205-212.
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IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2017-2025.
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Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011; 01/2011
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J. Solid-State Circuits. 01/2010; 45:751-758.
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IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
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IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
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Keith A. Bowman,
James W. Tschanz,
Shih-Lien Lu,
Paolo A. Aseron,
Muhammad M. Khellah,
Arijit Raychowdhury,
Bibiche M. Geuskens,
Carlos Tokunaga,
Chris Wilkerson, Tanay Karnik,
Vivek De
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010; 01/2010
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James Tschanz,
Keith A. Bowman,
Shih-Lien Lu,
Paolo A. Aseron,
Muhammad M. Khellah,
Arijit Raychowdhury,
Bibiche M. Geuskens,
Carlos Tokunaga,
Chris Wilkerson, Tanay Karnik,
Vivek De
IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010
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IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010
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James Tschanz,
Keith A. Bowman,
Muhammad M. Khellah,
Chris Wilkerson,
Bibiche M. Geuskens,
Dinesh Somasekhar,
Arijit Raychowdhury,
Jaydeep Kulkarni,
Carlos Tokunaga,
Shih-Lien Lu, Tanay Karnik,
Vivek De
Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010; 01/2010
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ABSTRACT: A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection se-quential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly com-plex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in man-aging metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%–32% throughput gain at equal V CC or at least 17% V CC reduction at equal throughput, corresponding to 31%–37% total power reduction.
IEEE Journal of Solid-State Circuits 01/2009; 44. · 3.23 Impact Factor
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Microelectronics Journal. 01/2009; 40:1523-1530.
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Donald S. Gardner,
Gerhard Schrom,
Peter Hazucha,
Fabrice Paillet, Tanay Karnik,
Shekhar Borkar,
Roy Hallstein,
Tony Dambrauskas,
Charles Hill,
Clark Linde,
Wojciech Worwag,
Robert Baresel,
Sriram Muthukumar
[show abstract]
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ABSTRACT: On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μH/mm2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability (>250 °C), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω, and quality factors up to 8 at frequencies as low as 40 MHz.
Journal of Applied Physics 03/2008; 103(7):07E927-07E927-6. · 2.17 Impact Factor
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9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA; 01/2008
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IEEE Trans. VLSI Syst. 01/2008; 16:1639-1647.
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8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA; 01/2007
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International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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IEEE Trans. Dependable Sec. Comput. 01/2004; 1:128-143.
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Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004; 01/2004
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Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002; 01/2002