Laurent Fournier

University of Haifa, H̱efa, Haifa District, Israel

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Publications (22)3 Total impact

  • Dorit Baras, Shai Fine, Laurent Fournier, Dan Geiger, Avi Ziv
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    ABSTRACT: Closing the feedback loop from coverage data to the stimuli generator is one of the main challenges in the verification process. Typically, verification engineers with deep domain knowledge manually prepare a set of stimuli generation directives for that purpose. Bayesian networks based CDG (coverage directed generation) systems have been successfully used to assist the process by automatically closing this feedback loop. However, constructing these CDG systems requires manual effort and a certain amount of domain knowledge from a machine learning specialist. We propose a new method that boosts coverage in the early stages of the verification process with minimal effort, namely a fully automatic construction of a CDG system that requires no domain knowledge. Experimental results on a real-life cross-product coverage model demonstrate the efficiency of the proposed method.
    International Journal on Software Tools for Technology Transfer 01/2011; 13:247-261.
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    Laurent Fournier, Avi Ziv, Ekaterina Kutsy, Ofer Strichman
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    ABSTRACT: Coverage is an important measure for the quality and completeness of the functional verification of hardware logic designs. Verification teams spend a significant amount of time looking for bugs in the design and in providing high-quality coverage. This process is performed through the use of various sampling strategies for selecting test inputs. The selection of sampling strategies to achieve the verification goals is typically carried out in an intuitive manner. We studied several commonly used sampling strategies and provide a probabilistic framework for assessing and comparing their relative values. For this analysis, we derived results for two measures of interest: first, the probability of finding a bug within a given number of samplings; and second, the expected number of samplings until a bug is detected. These results are given for both recurring sampling schemes, in which the same inputs might be selected repeatedly, and for nonrecurring sampling schemes, in which already sampled inputs are never selected again. By considering results from the theory of search, and more specifically, from the well-known multiarmed bandit problem, we demonstrate the optimality of a greedy sampling strategy within our defined framework.
    ACM Trans. Design Autom. Electr. Syst. 01/2011; 16:38.
  • Shai Fine, Laurent Fournier, Avi Ziv
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    ABSTRACT: Reaching hard-to-reach coverage events is a difficult task that requires both time and expertise. Data-driven coverage directed generation (CDG) can assist in the task when the coverage events are part of a structured coverage model, but is a priori less useful when the target events are singular and not part of a model. We present a data-driven CDG technique based on Bayesian networks that can improve the coverage of cross-product coverage models. To improve the capability of the system, we also present virtual coverage models as a means for enabling data-driven CDG to reach singular events. A virtual coverage model is a structured coverage model (e.g., cross-product coverage) defined around the target event, such that the target event is a point in the structured model. The CDG system can exploit this structure to learn how to reach the target event from covered points in the structured model. A case study using CDG and virtual coverage to reach a hard-to-reach event in a multi-processor system demonstrates the usefulness of the proposed method.
    International Journal on Software Tools for Technology Transfer 01/2009; 11:291-305.
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    Laurent Fournier, Avi Ziv
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    ABSTRACT: Reaching hard-to-reach coverage events is a difficult task that requires both time and expertise. Data-driven Coverage Directed Generation (CDG) can assist in the task when the coverage events are part of a structured coverage model, but is a-priori less useful when the target events are singular and not part of a model. We present virtual coverage models as a mean for enabling data-driven CDG to reach singular events. A virtual coverage model is a structured coverage model (e.g., cross-product coverage) defined around the target event, such that the target event is a point in the structured model. With the structured coverage model around the target event, the CDG system can exploit the structure to learn how to reach the target event from covered points in the structured model. A case study of using CDG and virtual coverage to reach a hard-to-reach event in a multi-processor system demonstrates the usefulness of the proposed method.
    02/2008: pages 104-119;
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    Dorit Baras, Laurent Fournier, Avi Ziv
    [show abstract] [hide abstract]
    ABSTRACT: Closing the feedback loop from coverage data to the stimuli generator is one of the main challenges in the verification process. Typically, verification engineers with deep domain knowledge manually prepare a set of stimuli generation directives for that purpose. Bayesian networks based CDG (coverage directed generation) systems have been successfully used to assist the process by automatically closing this feedback loop. However, constructing these CDG systems requires manual effort and a certain amount of domain knowledge from a machine learning specialist. We propose a new method that boosts coverage at early stages of the verification process with minimal effort, namely a fully automatic construction of a CDG system that requires no domain knowledge. Experimental results on a real-life cross-product coverage model demonstrate the efficiency of the proposed method.
    Hardware and Software: Verification and Testing, 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008. Proceedings; 01/2008
  • Laurent Fournier, Avi Ziv
    Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings; 01/2007
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    ABSTRACT: We present a framework for validating the compliance of a design with a given architecture. Our approach is centered on the concept of misinterpretations. These include missing behavior, wrong understanding of a behavior, or confusion with similar behavior described in the architecture or elsewhere. We formally capture the architecture behavior in the form of flowcharts and automatically derive a list of architecture misinterpretations from these flowcharts. These misinterpretations constitute the backbone of coverage models targeted by a suite of tests. The suite is automatically generated by a model-based test case generator. A compliance validation system based on these principles has been developed and used in two actual industrial processes of checking compliance with the PowerPC architecture.
    Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007; 01/2007
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    ABSTRACT: Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools' help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimidating and time-consuming task. This paper presents several techniques for coverage analysis. These techniques range from highly interactive and dynamic analysis that allows users to focus on certain aspects or areas of interest in the coverage model to fully automated coverage analysis, which identifies uncovered or lightly covered areas. The proposed techniques provide additional means for extracting relevant, useful information, thereby improving the quality of the coverage analysis. A number of examples show how the proposed method improved the verification of actual designs
    IEEE Transactions on Computers 12/2006; 55(11):1367-1379. · 1.38 Impact Factor
  • H. Azatchi, L. Fournier, A. Ziv, K. Zohar
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    ABSTRACT: Coverage analysis is used to monitor the quality of the verification process. Reports provided by coverage tools help users identify areas in the design that have not been adequately tested. Because of their sheer size, the analysis of large coverage models can be an intimidating and time-consuming task. This paper presents two new techniques for coverage analysis. The first technique, coverage query, allows users that concentrate on a single uncovered event to find larger phenomena (e.g., hole) that contains this event. The second technique, quasi-hole analysis, automatically identifies large areas in the coverage space that are lightly covered. The proposed techniques provide additional means for extracting relevant, useful information, thereby improving the quality of the coverage analysis. A number of examples are provided showing how the proposed method improved the verification of actual designs.
    High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International; 01/2006
  • IEEE Trans. Computers. 01/2006; 55:1367-1379.
  • Allon Adir, Laurent Fournier, Yoav Katz, Anatoly Koyfman
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    ABSTRACT: This paper presents a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs and increasing the need for such technology. DeepTrans is a package that extends existing test generators with address translation testing capabilities. It uses a declarative modeling language that includes constructs for describing the address translation process, commonly used translation resources, and architecture rules related to translation. The address translation model is converted to a constraint satisfaction problem that is solved simultaneously with the problem formulated by the generator. DeepTrans is currently used by two different IBM test generators
    01/2006;
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    ABSTRACT: Functional verification is widely recognized as the bottleneck of the hardware design cycle. With the ever-growing demand for greater performance and faster time to market, coupled with the exponential growth in hardware size, verification has become increasingly difficult. Although formal methods such as model checking and theorem proving have resulted in noticeable progress, these approaches apply only to the verification of relatively small design blocks or to very focused verification goals. Current industry practice is to use separate, automatic, random stimuli generators for processor- and multiprocessor-level verification. The generated stimuli, usually in the form of test programs, trigger architecture and microarchitecture events defined by a verification plan. MAC-based algorithms are well suited for the test program generation domain because they postpone heuristic decisions until after consideration of all architectural and testing-knowledge constraints. Geneysys-Pro is currently the main test generation tool for functional verification of IBM processors, including several complex processors. We've found that the new language considerably reduces the effort needed to define and maintain knowledge specific to an implementation and verification plan.
    IEEE Design and Test of Computers 04/2004; · 1.62 Impact Factor
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    ABSTRACT: FPgen is a new test generation framework targeted toward the verification of the floating point (FP) datapath, through the generation of test cases. This framework provides the capacity to define virtually any architectural FP coverage model, consisting of verification tasks. The tool supplies strong constraint solving capabilities, allowing the generation of random tests that target these tasks. We present an overview of FPgen's functionality, describe the results of its use for the verification of several FP units, and compare its efficiency with existing test generators.
    High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International; 12/2003
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    Avi Ziv, Laurent Fournier
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    ABSTRACT: The mathematical problem discussed is important for generating test cases in order to debug floating point adders designs.Floating point numbers are assumed to be written as strings of {0,1} bits, in a format compatible with IEEE standard 754. A mask is a string of characters, composed of {‘0’, ‘1’, ‘x’}. A number and a mask are compatible if they have the same length and each numerical character of the mask (‘0’ or ‘1’) is equal, numerically, to the bit of the number, in the same position. The problem discussed is: Given masks Ma, Mb, Mc, of identical lengths, generate three floating point numbers ā, b̄, c̄, which are compatible with the masks and satisfy c̄=round(ā±b̄). If there are many solutions, choose one at random. A fast algorithm is given which solves the problem for all IEEE floating point data types and all rounding modes.
    Theor. Comput. Sci. 01/2003; 291:183-201.
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    Laurent Fournier, Anatoly Koyfman, Moshe Levinger
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    ABSTRACT: This paper describes the efforts made and the results of creating an Architecture Validation Suite for the PowerPC architecture. Although many functional test suites are available for multiple architectures, little has been published on how these suites are developed and how their quality should be measured. This work provides some insights for approaching the difficult problem of building a high quality functional test suite for a given architecture. By defining a set of generic coverage models that combine program-based, specification-based, and sequential bug-driven models, it establishes the groundwork for the development of architecture validation suites for any architecture.
    12/2002;
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    ABSTRACT: A central problem in automatic test generation is solving constraints for memory access generation. A framework, and an algorithm that has been implemented in the Model-Based Test-Generator are described. This generic algorithm allows flexibility in modeling new addressing modes with which memory accesses are generated. The algorithm currently handles address constraint satisfaction for complex addressing modes in the PowerPC, x86, and other architectures.
    12/2002;
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    Abraham Ziv, Laurent Fournier
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    ABSTRACT: The mathematical problem discussed is important for generating test cases in order to debug floating point adders designs.
    12/2002;
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    L. Fournier, Y. Arbetman, M. Levinger
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    ABSTRACT: Even though the importance of microprocessor design verification is widely acknowledged, no rigorous methodology is being commonly followed for its realization. This paper attempts to delineate such a methodology, and shows how it is promoted by Genesys, an automatic pseudo-random test-program generator. The methodology relies on a verification plan which induces smart sets of tests that carry out the verification tasks. The paper reports on an application of this methodology, using Genesys, to verify an x86 design and describes, in particular, how this methodology could have helped to avoid known escape bugs, such as the recent two infamous Pentium Floating Point bugs
    Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings; 02/1999
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    Laurent Fournier, Yaron Arbetman, Moshe Levinger
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    ABSTRACT: An abstract is not available.
    01/1999;
  • L. Fournier, Y. Arbetman, M. Levinger
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    ABSTRACT: This paper delineates a rigorous methodology for microprocessor design verification, and shows how it is promoted by Genesys, an automatic pseudo-random test-program generator. The paper reports on an application of this methodology, using Genesys, to verify an x86 design. The principal contribution of this work is to set the general guidelines for obtaining a compound functional verification framework, and to describe how this can be optimally implemented by a test-program generator such as Genesys. The goal of the paper is to assist in the composition of verification processes which typically include only part of the testing suggested in this framework.
    2008 Design, Automation and Test in Europe. 01/1999;