Dukmin Kwon

Publications (4)3.23 Total impact

• Conference Proceeding: A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW.

  Hoeju Chung, Byung-Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, [......], HoGeun Cho, Inchul Shin, Woochul Jun, Seokwon Hwang, Ki-Whan Song, KwangJin Lee, Sang-whan Chang, Woo-Yeong Cho, Jei-Hwan Yoo, Young-Hyun Jun
  IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
• Article: 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

  Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, Duk-Ha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, [......], Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo Sun Choi, Changhyun Kim, Young-Hyun Jun
  [show abstract] [hide abstract]
  ABSTRACT: An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.
  IEEE Journal of Solid-State Circuits 02/2010; · 3.23 Impact Factor
• Article: 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.

  Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, [......], Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun
  J. Solid-State Circuits. 01/2010; 45:111-119.
• Conference Proceeding: 8Gb 3D DDR3 DRAM using through-silicon-via technology.

  Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, [......], So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim
  IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009