[show abstract][hide abstract] ABSTRACT: Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these computation needs, only multithreaded approaches are possible. Thus, the support of a streaming execution model is very important for dataflow applications. However, with dynamic applications, each execution stage is prone to execution time variations. The sizing of these highly complex MPSoC architectures becomes difficult. In such a context, flexible and accurate simulators become a necessity for exploring the vast design space solution. In this paper, we use the SESAM environment to ease the architectural exploration of asymmetric MPSoCs for dynamic streaming application processing. This paper focuses on the new programming and execution model supported by the simulator, and studies performances obtained with a WCDMA encoder/decoder application implemented on a complete MPSoC platform.
VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP; 10/2010
[show abstract][hide abstract] ABSTRACT: Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase in the design complexity of MPSoC architectures that must support these constraints, flexible and accurate simulators become a necessity for exploring the vast design space solutions. In this paper, we present an asymmetric MPSoC simulator environment, named SESAM. This tool can be used for the architecture exploration and optimization, and the design of a complete MPSoC solution for dynamic application processing. Its performances and capabilities are demonstrated through a complete MPSoC platform and an implementation of the component labeling algorithm.
Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on; 08/2010
[show abstract][hide abstract] ABSTRACT: As application complexity grows, embedded systems move to multiprocessor architectures to cope with the computation needs.
The issue for multiprocessor architectures is to optimize the processing resources usage and power consumption to reach a
higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue we propose a global
online scheduling algorithm for streaming applications. It takes into account data dependencies between pipeline tasks to
optimize processor usage and reduce power consumption through the use of DPM and DVFS modes. An implementation of the algorithm
on a virtual platform, executing a WCDMA application, demonstrates up to 45% power consumption gain while guaranteeing regular
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers; 01/2010