Publications (3)0 Total impact
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Conference Proceeding: Reducing verification overhead with RTL slicing.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007; 01/2007 -
Conference Proceeding: Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.
19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India; 01/2006 -
Conference Proceeding: An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005; 01/2005
Institutions
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2007
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Synopsys
Mountain View, CA, USA
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