[show abstract][hide abstract] ABSTRACT: Nanoelectronics constructed by nanoscale devices seems promising for the advanced development of integrated circuits (ICs). However, the lack of computer aided design (CAD) tools seriously hinders its development and applications. To investigate the cell mapping task in CAD flow, we present a genetic algorithm (GA) based method for Cmos/nanowire/MOLecular hybrid (CMOL), which is a nanohybrid circuit architecture. By designing several crossover operators and analyzing their performance, an efficient crossover operator is proposed. Combining a mutation operator, a GA based algorithm is presented and tested on the International Symposium on Circuits and Systems (ISCAS) benchmarks. The results show that the proposed method not only can obtain better area utilization and smaller delay, but also can handle larger benchmarks with CPU time improvement compared with the published methods.
Journal of Computer Science and Technology 01/2012; 27:113-120. · 0.48 Impact Factor
[show abstract][hide abstract] ABSTRACT: By mapping a fixed polarity Reed-Muller (RM) expression into an onset table and studying the properties of the onset table,
an algorithm is proposed to obtain a compact multi-level single-output mixed-polarity RM function by searching for and extracting
the common variables using the onset table. Furthermore, by employing the multiplexer model, the algorithm is extended to
optimize multi-level multi-output mixed-polarity RM forms. The proposed algorithm is implemented in C language and tested
using some MCNC benchmarks. Experimental results show that the proposed algorithm can obtain a more compact RM form than that
under fixed polarity. Compared with published results, the proposed algorithm makes a significant speed improvement, with
a small increase in the number of literals.
Key wordsLogic optimization–Reed-Muller functions–Multi-level–Mixed polarity–Onset table
Journal of Zhejiang University: Science C 01/2011; 12(4):288-296. · 0.30 Impact Factor
[show abstract][hide abstract] ABSTRACT: This paper considers a cell mapping task of CMOL, a hybrid CMOS/molecular circuit architecture. To tackle the combinatorial hurdle arising from the structural connectivity domain constraint, a memetic computing algorithm is developed. The framework takes advantage of simulated annealing based local search strategy and appropriate population based encoding manipulation. Numerical results from ISCAS benchmarks and comparison with pure genetic approach illustrate the effectiveness of the modeling and solution methodology. In terms of CPU runtime, timing delay and circuit scale, the proposed method has better performance than previous methods.
13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France; 01/2010
[show abstract][hide abstract] ABSTRACT: Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for
mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum
shrinkage (GSS), elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented
to derive a compact Multi-level Mixed Polarity Reed-Muller Form (MMPRMF) starting from a given fixed polarity truth vector.
The results show that a significant area improvement can be made compared with published results.
Journal of Computer Science and Technology 10/2005; 20(6):895-900. · 0.48 Impact Factor
[show abstract][hide abstract] ABSTRACT: A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
Journal of Computer Science and Technology 02/2005; 20(2):237-242. · 0.48 Impact Factor