Yuan-Tzu Ting

Chung Shan Institute of Science and Technology, Hsin-chu-hsien, Taiwan, Taiwan

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Publications (7)3.53 Total impact

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    Shyh-Jye Jou, Yuan-Tzu Ting
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    ABSTRACT: This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100# stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length.
    05/1997;
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    ABSTRACT: In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic effects in an analog testability bus test environment. For the test response analysis, we derive an extraction methodology to remove the parasitic effects and obtain the intrinsic response of the CUT. The test results show that the algorithm is robust such that the intrinsic responses remain the same regardless of the small variation in the test waveforms. With the concept of intrinsic responses, we are able to use a single library for the testing and diagnosis of multiple instantiation of an analog module
    Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on; 12/1996
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    ABSTRACT: An n+-GaAs/nāˆ’-GaAs/n-In0.2Ga0.8As/i-GaAs field-effect transistor (FET) structure has been fabricated and studied. An anomalous three-terminal-controlled negative-differential-resistance (NDR) phenomenon resulting from the real-space transfer effect is observed. This N-shaped NDR behavior is found in the higher drain-to-source voltage (VDS) regime. Furthermore, the NDR is obtained at positive and negative gate-to-source bias (VGS). The influence ofVGSbias on the NDR characteristics is investigated.
    Superlattices and Microstructures 06/1996; 20(1):7ā€“13. · 1.98 Impact Factor
  • Source
    Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting
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    ABSTRACT: This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length
    European Design and Test Conference, 1996. ED&TC 96. Proceedings; 04/1996
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    ABSTRACT: In this paper, we present a syndrome test methodology for the testing of unscanned interconnects in a boundary scan environment. Mathematical equations are derived for the relationship of test length, fault-free and faulty syndromes, and tolerable error rate. To calculate fault-free and faulty syndromes, we propose an event driven syndrome simulation algorithm. To shorten testing time and reduce test cost, we transform and solve the problem as a set covering problem.
    Proceedings of the Asian Test Symposium 01/1996;
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    Yuh-Maoh Sun, Meng-Chyi Wu, Yuan-Tzu Ting
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    ABSTRACT: In this article, we report the growth of GaSb layers by introducing the rare earth element Er into Sb-rich GaSb liquid phase epitaxy solutions. We find that the carrier concentration of GaSb layers can be effectively lowered due to the gettering of residual impurities and the suppression of complex acceptor defects in the presence of Er. Three intense sharp lines consisting of free exciton (FE) and excitons bound to neutral acceptors (BE3 and BE4) dominate the low temperature photoluminescence spectra of Er-doped GaSb. Zn-diffused Er-doped GaSb diodes exhibit higher contact resistances and breakdown voltages due to lower carrier concentration than for equivalent undoped diodes.
    Journal of Crystal Growth 01/1996; 158(4):449-454. · 1.55 Impact Factor
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    ABSTRACT: In this paper we fabricate a GaAs/n<sup>+</sup>InGaAs/GaAs doped-channel FET device with significant transistor performance. The use of the doped-channel structure also has the benefits of: (1) enhanced electron mobility and velocity in the InGaAs channel; and (2) elimination of the undesired DX centers or persistent photoconductivity effect. Study of the structure reveals that it exhibits the anomalous negative differential resistance (NDR) phenomenon. We conclude that the NDR performance is related to the existence of deep-level electron traps and the real-space transfer effect. Because only part of the fabricated devices exhibit NDR phenomena, the nonuniformly distributed deep-level electron traps related to the substrate or MOCVD growth process may be expected. The existence of electron traps enhances the decrease of channel current resulting from the real-space transfer effect. When the channel electrons gain enough energy from the accelerating field (at higher V<sub>DS</sub> regime), they may inject into the neighboring GaAs layers and become trapped in the deep levels. This causes the reduction of conduction current and occurrence of NDR behavior
    Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on; 12/1995

Publication Stats

32 Citations
3.53 Total Impact Points

Institutions

  • 1996
    • Chung Shan Institute of Science and Technology
      Hsin-chu-hsien, Taiwan, Taiwan
    • National Central University
      • Department of Electrical Engineering
      Taoyuan City, Taiwan, Taiwan