[Show abstract][Hide abstract] ABSTRACT: It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year.  However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 (16.79 mm 10.68 mm) in 3 metal 26 nm CMOS.
Journal of Semiconductor Technology and Science 01/2011; 11(2). · 0.58 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost. However, these devices suffer from program performance degradation since tighter Vth distribution is required. On the other hand, area scaling is a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome, such as FG coupling and charge retention. As the cell size gets smaller, the Vth distribution widens and the erase-write cycling margin is decreased by the floating-gate coupling ratio.
IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011