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ABSTRACT: Network on Chip (NoC) is considered to be the best candidate for future on-chip communication; however, with the increase in the number of on-chip processors, the simultaneous memory accesses of these processors can cause serious main memory bottleneck problem. In this study, we have proposed the concept of Network Main Memory (NMM). NMM has distributed network architecture for main memory and multicommunication channels to NoC chips, which can overcome the main memory bottleneck problem. When compared with traditional memory, the bandwidth of NMM can be sufficiently used owing to the network architecture, and it is convenient to increase the memory bandwidth. Our experimental results on simulator show that our NMM can provide better traffic for NoCs. In addition, management of NMM as well as the software model for NoC chips and NMM have also been discussed.
Computer and Information Technology (CIT), 2010 IEEE 10th International Conference on; 08/2010
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10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010; 01/2010
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Fifth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2008, 18-20 October 2008, Jinan, Shandong, China, Proceedings, Volume 5; 01/2008
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The Second International Conference on Future Generation Communication and Networking, FGCN 2008, Volume 2, Workshops, Hainan Island, China, December 13-15, 2008; 01/2008
