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ABSTRACT: An integrated current-feedback variable-gain amplifier (VGA) suitable for low-power ultrasound diagnostic applications is
presented in this paper, which provides variable gain to accommodate large input dynamic range of ultrasonic receiver. With
a proposed active feedback technique, the amplifier maintains a constant bandwidth at different gain levels. Signal distortion
due to the bandwidth shift is thus avoided. Compared to most Bipolar and BiCMOS counterparts, the proposed VGA is implemented
in a low-cost CMOS process, without compromising the performance. In addition, it employs a resistive feedback network to
automatically set the output DC voltage, without using any extra common-mode feedback (CMFB) circuits, making the design simple
and effective. The proposed VGA was fabricated and tested with a standard 0.35-μm CMOS process, with an active die area of
only 0.052mm2. The static power dissipation is 2.18mW with a power supply of 3.0V. The VGA exhibits a constant bandwidth of 4.5MHz with
a variable gain ranging from 0 to 46dB. The system is well stabilized with a phase margin of 71.3° at the worst case. Comparisons
to the state-of-the-arts demonstrate very competitive performance of this work.
Analog Integrated Circuits and Signal Processing 04/2012; 61(2):171-179. · 0.59 Impact Factor
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ABSTRACT: A power-efficient, high-frequency, automatic reconfigurable switching converter is presented in this paper for DVS-enabled VLSI systems. Tailored to the system-level power management, the proposed cross-layered green-mode (GM) operation scheme adaptively configures the converter into three operation structures to achieve a seamless step-up/down voltage conversion with minimized power loss. In addition, an adaptive power transistor sizing (APTS) scheme is incorporated to further improve efficiency on the transistor level. To enable high-frequency operation in all power regulation conditions, an i <sub>L</sub>-assisted single-bound hysteresis controller (SBHC) is also proposed in this work. Meanwhile, in order to suppress output spectrum variations induced by the hysteresis controller, an adaptive frequency compensator (AFC) is employed. The proposed converter was fabricated with IBM 130-nm CMOS process, with a total chip area of 1 mm<sup>2</sup>. Its output voltage can be seamlessly regulated from 0.9 to 2.2 V, with a maximum load power of 400 mW. The input voltage is designed at 1.5 V, but is variable at any level between 0.9 and 1.8 V. The switching frequency of the converter is regulated at 10 MHz in all three operation modes, with ±3% deviation. Experimental results show a 26.7- μs/V down-tracking and 93.3-μs/V up-tracking speed for dynamic voltage scaling (DVS) reference tracking. Line regulation is maintained below 0.8% throughout the full input voltage range, with a lowest value of 0.17%. The power efficiency stays above 80% over the entire 400-mW power range, with a peak value of 92.1% at 1.2-V output and 250-mW load power.
IEEE Journal of Solid-State Circuits 07/2011; · 3.23 Impact Factor
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IEEE Trans. on Circuits and Systems. 01/2011; 58-II:376-380.
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IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2790-2800.
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IEEE Trans. on Circuits and Systems. 01/2011; 58-I:2377-2387.
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ABSTRACT: A green-mode power converter is implemented in 0.13 ¿m CMOS and achieves step-up/down variable output with adaptively optimized efficiency. Single-bound hysteresis control enables high-frequency switching regulation with suppressed error and noise. For V<sub>m</sub> = 1.5 V and f<sub>s</sub> = 10 MHz, the output is regulated from 0.9 to 2.2 V with an efficiency of >80% over a 400 mW power range.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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IEEE Trans. on Circuits and Systems. 01/2010; 57-II:686-690.
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ABSTRACT: An integrated switching DC-DC power converter is proposed to implement an adaptive wireless powering scheme in implantable biomedical devices. The proposed dual-loop Δ-Σ modulation, error correction and noise shaping techniques work jointly to improve the transient response, noise suppression and line regulation performances. An observation-based double-sampling (OBDS) sensor and a double-sampling half-clock (DSHC) 1-bit A/D converter are also introduced to further increase the signal processing speed without causing any extra cost. The converter was designed with a standard 130-nm CMOS process. The fully transistor-based HSPICE simulation results demonstrate a 2.8/2.2-μs up/down tracking time to a full-range reference voltage step change. A 7.95-mV/V line regulation is achieved, when the supply voltage varies from 1.1 V to 1.5 V. With a 1.2-V supply, the maximum efficiency of 95.5% is measured at 0.9-V output voltage and 90-mW load power, while the efficiency stays above 80% over the entire 170-mW load power range.
Industrial Electronics, 2009. IECON '09. 35th Annual Conference of IEEE; 12/2009
