[Show abstract][Hide abstract] ABSTRACT: As VLSI designs grow in complexity and size, errors become more frequent and difficult to track. Recent developments have automated most of the verification tasks but debugging still remains a resource-intensive, manually conducted procedure. This paper bridges this gap as it develops robust automated debugging methodologies that complement verification processes. Unlike prior debugging techniques, the proposed one exploits the hierarchical nature of modern designs to improve the performance and quality of debugging. It also formulates the problem in terms of Quantified Boolean Formula Satisfiability to obtain dramatic reduction in memory requirements, which allows for debugging of large designs. Extensive experiments conducted on industrial and benchmark designs confirm the efficiency and practicality of the proposed approach
Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on; 12/2005
[Show abstract][Hide abstract] ABSTRACT: Recent advances in Boolean satisabilit y have made it attractive to solve many digital VLSI design problems such as verication and test generation. Fault diag- nosis and logic debugging have not been addressed by existing satisabilit y-based solutions. This paper at- tempts to bridge this gap by proposing a model-free satisabilit y-based solution to these problems. The proposed formulation is intuitive and easy to imple- ment. It shows that satisabilit y captures signican t problem characteristics and it oers dieren t trade-os. It also provides new opportunities for satisabilit y- based diagnosis tools and diagnosis-specic satisabil- ity algorithms. Theory and experiments validate the claims and demonstrate its potential.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2005; 24:1606-1621. DOI:10.1109/MTV.2003.1250264 · 1.00 Impact Factor
[Show abstract][Hide abstract] ABSTRACT: Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean satisfiability. This formulation takes advantage of modern Boolean satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean satisfiability provides an effective platform for sequential logic debugging.
Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA; 01/2004