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ABSTRACT: Abstract Fetal electrocardiogram (ECG) extraction from non-invasive biopotential recordings is a long-standing research topic. Despite the significant number of algorithms presented in the scientific literature, it is difficult to find information about embedded hardware implementations able to provide real-time support for the required features, bridging the gap between theory and practice. This article presents the NInFEA (non-invasive fetal ECG analysis) tool, an embedded hardware/software framework based on the hybrid dual-core OMAP-L137 low-power processor for the real-time evaluation of fetal ECG extraction algorithms. The hybrid platform, including a digital signal processor (DSP) and a general-purpose processor (GPP), allows achieving the best performance compared with single-core architectures. The GPP provides a portable graphical user interface, whereas the DSP is extensively used for advanced signal processing tasks. As a case study, three state-of-the-art fetal ECG extraction algorithms have been ported onto NInFEA, along with some support routines needed to provide the additional information required by the clinicians and supported by the user interface. NInFEA can be regarded both as a reference design for similar applications and as a common embedded low-power testbed for real-time fetal ECG extraction algorithms.
Biomedizinische Technik/Biomedical Engineering 12/2012; · 0.53 Impact Factor
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IEEE Trans. Biomed. Circuits and Systems. 01/2011; 5:368-379.
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2011 Conference on Design and Architectures for Signal and Image Processing, DASIP 2011, Tampere, Finland, November 2-4, 2011; 01/2011
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Proceedings of the 8th Conference on Computing Frontiers, 2011, Ischia, Italy, May 3-5, 2011; 01/2011
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ABSTRACT: Self organization is the property of some natural systems to organize themselves without a central coordination unit to perform
specific tasks. Swarm Intelligence is a bioinspired paradigm coming from the observation of natural swarms, such as honey
bees and bird flocks. Swarms exploit self organization to achieve coordination, speed-up and fault tolerance. This interesting
paradigm has been applied in different research fields, mainly in robotics and optimization algorithms. Our pioneering studies
about the application of this powerful paradigm to digital VLSI systems demonstrated that Swarm Intelligence can be applied
to the design of scalable computing architectures composed of a large set of self-coordinated hardware agents. In this Chapter
we present this approach with a review of our research works in this field from the first explorations to the latest results:
the FPGA implementation of a coprocessing architecture expressly conceived resorting to the Swarm Intelligence principles.
Some experimental results are presented to evaluate the main features of this innovative approach, which shows interesting
performance improvements without any programming effort and without complex tools for compilation and mapping, compared to
other state-of-the-art coprocessing architectures.
01/2010: pages 91-112;
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Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010; 01/2010
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NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010; 01/2010
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ABSTRACT: The Reconfigurable Video Coding (RVC) framework is a recent ISO standard aiming at providing a unified specification of MPEG video technology in the form of a library of components. The word “reconfigurable” evokes run-time instantiation of different decoders starting from an on-the-fly analysis of the input bitstream. In this paper we move a first step towards the definition of systematic procedures that, based on the MPEG RVC specification formalism, are able to produce multi-decoder platforms, capable of fast switching between different configurations. Looking at the similarities between the decoding algorithms to implement, the papers describes an automatic tool for their composition into a single configurable multi-decoder built of all the required modules, and able to reuse the shared components so as to reduce the overall footprint (either from a hardware or software perspective). The proposed approach, implemented in C++ leveraging on Flex and Bison code generation tools, typically exploited in the compilers front-end, demonstrates to be successful in the composition of two different decoders MPEG-4 Part 2 (SP): serial and parallel.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, DASIP 2010, Edinburgh, Scotland, UK, October 26-28, 2010, Electronic Chips & Systems design Initiative, ECSI; 01/2010
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ABSTRACT: Self-organization is the property of some natural systems to organize themselves without a central coordination unit to perform
specific tasks. In this paper, the FPGA prototype of a digital architecture based on a bio-inspired coprocessor for fixed-point
array processing is presented. The coprocessor is designed around a tiled architectures resorting to the principles of Swarm
Intelligence to perform the assigned tasks with simultaneous adaptive multitasking capabilities exploiting cooperative behaviors
and self-organization, without any hardware configuration. Profiling results on some sample application shows performance
improvements up to 36 times with respect to the execution on the processor only.
03/2008: pages 149-158;
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ABSTRACT: Massively Parallel Processors on-Chip, presenting the same problems of their non-monolithic counterparts, exacerbated by the
limited on-chip resources, are the most challenging architectures in the processor architectures domain. In this paper, a
novel nature-inspired decentralized algorithm, aiming at the definition of clusters of processors to be assigned to different
threads, is presented and evaluated. Taking inspiration from liquid surface tension and drops coalescence, the proposed solution
achieves better performances than other distributed solutions, reducing fragmentation and communication latency within the
clusters.
03/2008: pages 335-345;
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Proceedings of the First International Conference on Health Informatics, HEALTHINF 2008, Funchal, Madeira, Portugal, January 28-31, 2008, Volume 2; 01/2008
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Proceedings of the First International Conference on Biomedical Electronics and Devices, BIOSIGNALS 2008, Funchal, Madeira, Portugal, January 28-31, 2008, Volume 2; 01/2008
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11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008; 01/2008
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Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings; 01/2008
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ABSTRACT: A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable
datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural
template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized)
for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has
been synthesized using Synopsys Design Compiler on a standard-cell 0.18 μ m technology. Estimated number of transistors is
335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles
and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to
95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles.
Journal of VLSI Signal Processing 07/2006; 44(1):135-152. · 0.73 Impact Factor
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Ant Colony Optimization and Swarm Intelligence, 5th International Workshop, ANTS 2006, Brussels, Belgium, September 4-7, 2006, Proceedings; 01/2006
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ABSTRACT: Starting from the observation of natural systems, bio-inspired collaborative schemes exploit the power of a fully decentralized
control to perform complex tasks. Currently this approach concerns software and robotic systems. In this paper we apply a
such approach to the VLSI implementation of the basic task in DSP systems: the summation of products. We analyze such operation
in terms of parallel distributed computation, showing how such reformulation can take advantages from the cooperation between
cells of a small colony. The interaction among cells, based on simple social rules, leads to a full exploitation of cells
computational capabilities obtaining a more efficient usage of their computational resources in a so important task. A preliminary
VLSI implementation and theoretical results are presented to show the feasibility of this approach.
12/2004: pages 362-371;
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Parallel Problem Solving from Nature - PPSN VIII, 8th International Conference, Birmingham, UK, September 18-22, 2004, Proceedings; 01/2004
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Ant Colony Optimization and Swarm Intelligence, 4th International Workshop, ANTS 2004, Brussels, Belgium, September 5 - 8, 2004, Proceedings; 01/2004
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ABSTRACT: Parallel implementations are widely used in digital architectures to enhance computational performances, exploiting the number of involved processing units. Cooperative behaviors typical of swarm intelligence can enhance the performances of such systems introducing an amplification effect due to the collective effort of a set of interacting hardware agents. Cooperation can also be exploited like a new weapon to achieve the fault-tolerance goal, with no need for expressly inserted redundant hardware resources. In this paper we present a novel architecture able to address these issues exploiting all the potentiality exposed by this bioinspired approach. A first implementation on CMOS technology shows the feasibility of such a design style, allowing preliminary simulations and discussions.
Journal of Parallel and Distributed Computing.
