Kazuyuki Wada

Toyohashi University of Technology, Toyohasi, Aichi, Japan

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Publications (21)4.45 Total impact

  • I. Akita, K. Wada, Y. Tadokoro
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    ABSTRACT: This paper presents a 100-kHz fifth-order Chebychev low-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequency tuning system based on the voltage-controlled-filter (VCF) architecture and voltage reference circuit, is fabricated in a 0.18-mum standard CMOS technology with a 0.5-V threshold voltage and consumes 443 muW from a power supply of 0.6 V. The output noise and the in-band IIP<sub>3</sub> are 575 pA<sub>rms</sub> and 219 muA, respectively. The filter achieves a dynamic range of 89 dB.
    IEEE Journal of Solid-State Circuits 11/2009; · 3.06 Impact Factor
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    ABSTRACT: This paper proposes structures of multi-path filters robust to substrate noise and nonlinearity of elements under low supply voltage to achieve wide dynamic range. They are derived by combining two structures which have been known to suppress substrate noise and nonlinearity more than the balanced one. Dynamic ranges and substrate noises of three proposed structures, the balanced (two-path) one, and the single ended (one-path) one are examined and simulation results show that the proposed structures reduce substrate noise and nonlinearity more than the conventional structures.
    International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan; 01/2009
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    ABSTRACT: A substrate noise cancellation circuit using cancellation points is proposed. Noise characteristic of a conventional cancellation circuit with divided points is analytically explained. A new version of active cancellation circuit with some points removed is proposed. Noise reduction of this version of active cancellation circuits is confirmed by computer simulations. Simulation and experimental results show using two cancellation points effectively reduces the noise.
    IEEJ Transactions on Electronics Information and Systems 01/2009; 129(8):1527-1533.
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    ABSTRACT: An active cancellation circuit using two detection bands for large digital circuit is proposed. A variation of an optimum transconductance of cancellation amplifier for a noise source position on the proposed circuit becomes smaller than that on the conventional circuit. Noise reduction effects of the new version of active cancellation circuits are confirmed by computer simulations.
    Communications, Control and Signal Processing, 2008. ISCCSP 2008. 3rd International Symposium on; 04/2008
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    ABSTRACT: A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-mum CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.
    IEICE Transactions. 01/2008; 91-A:535-541.
  • Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
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    ABSTRACT: A scheme for a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range is proposed and its prototype is presented. A nodal voltage which is fixed in a conventional filter based on the dynamically adjustable biasing (DAB) technique is adapted for change of input envelope to achieve wide dynamic range. Externally linear and time invariant (ELTI) relation between an input and an output is guaranteed by a state variable correction (SVC) circuit which is also proposed for low-voltage operation. To demonstrate the proposed scheme, a fifth-order Chebychev low-pass filter with 100-kHz cutoff frequency is designed and fabricated in a standard 0.35-μm CMOS process. The filter has a 78-dB dynamic range and consumes 200-μW power from a 0.8-V power supply.
    IEICE Transactions. 01/2008; 91-C:87-95.
  • I. Akita, K. Wada, Y. Tadokoro
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    ABSTRACT: This paper proposes a low-voltage syllabic companding log domain filter without state variable correction circuits, which is needed for externally linear and time-invariant operation of conventional filters. The proposed filter is simplified and has wide input range under low-supply voltage by varying a nodal voltage adaptively. The simulation results show 60-dB input range for over 40-dB signal to noise plus distortion ratio at a power supply of 0.6 V in a 0.18-mum CMOS process.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007
  • Source
    IEICE Transactions. 01/2007; 90-A:372-379.
  • Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro
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    ABSTRACT: This paper proposes a synthesis method of all low-voltage CMOS instantaneous-companding log domain integrators. The method is based on the exhaustive search of all low-voltage CMOS instantaneous-companding log domain integrators. All the integrators are derived from a general block diagram. A function of each block can be realized by any of a family of circuits and elemental circuits chosen from such families are combined to build an integrator. It is clarified that each family contains a few circuit topologies. All topologies of integrators including new ones are obtained from combinational procedure. Comparing characteristics of all generated integrators, ones satisfying required performances are found out.
    IEICE Transactions. 01/2007; 90-A:339-350.
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    I. Akita, K. Wada, Y. Tadokoro
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    ABSTRACT: This paper presents a low-voltage CMOS syllabic-companding log domain filter with wide dynamic range. The proposed filter is synthesized based on the idea of varying a voltage which is fixed on a dynamically adjustable biasing (DAB) filter. A low-voltage envelope detector necessary for a DAB filter is also designed including quantization mechanism. Simulation results show the proposed filter is effective in widening dynamic range
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 06/2006
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    ABSTRACT: Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises with different signs outside of a guard ring. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by the two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation results show that the proposed band connections reduce the noise
    International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
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    ABSTRACT: An active shield circuit which effectively reduces the substrate noise on the entire area inside the guard ring regardless of the noise source position is proposed. Simulation result shows that the proposed circuit can reduce the noise level to -85 dB while a conventional guard ring gives -52 dB.
    IEICE Transactions. 01/2005; 88-A:438-443.
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    ABSTRACT: A design optimization of active shield circuit using noise averaging method is proposed. The relation between the averaged noise and the design parameters of the active shield circuit such as circuit gain and on-chip layout is examined. A simple design guideline is also provided. Simulation results show that the active shield circuit designed by the proposed optimization method gives a better noise suppression performance of about 28% than the conventional one.
    IEICE Transactions. 01/2005; 88-A:444-450.
  • K. Wada, Y. Tadokoro
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    ABSTRACT: This paper proposes a design of RC polyphase filters with flat gain characteristics in the passband and equi-ripple ones in the stopband. The time constants of cascaded sections are given by an equation in explicit form. Resistances and capacitances for optimum filters are obtained by solving an equation which is a polynomial of only one unknown parameter. Design examples are shown and effectiveness of the design is confirmed from simulation results.
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on; 06/2003
  • K. Wada, Y. Tadokoro
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    ABSTRACT: A scheme reducing error on source followers due to the body effect is proposed. A node of a source follower which has been connected to a DC voltage source is excited by a control circuit so that an output signal is well compensated. The scheme employs an additional source follower for detecting error of an original source follower. Since the error is algebraically analyzed, a characteristic of a control circuit for tuning the node potential is solved. Based on the scheme a level-shift circuit is given and its effectiveness is confirmed through computer simulations and application to the bias-offset technique.
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on; 02/2002
  • Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
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    ABSTRACT: ln the design of integrator-based filters, there are degrees of freedom in selection of the signal flow graph representing the connection state of the integrator. In this paper, a procedure is proposed for selecting the signal flow graph for a filter with a small deviation from the ideal frequency characteristics. In general, the integrator works ideally near the unit-gain frequency. Hence, in order to realize a filter with excellent characteristics, a guideline is described for selecting the signal flow graph such that the unit-gain frequencies of all integrators used in the filter are close to each other. Since the amount of computation for selection of the signal flow graph becomes enormous even in a filter of low order, an evaluation scale for search is used that can easily estimate the spread of the unit-gain frequencies in individual signal flow graphs. As examples, the signal flow graphs are derived for the fifth-order maximally flat-delay low-pass filter and the third-order amplitude equal-ripple low-pass filter. The validity of the proposed evaluation scale is presented. The effectiveness of the design guideline is confirmed by a computer simulation of the filter made up of MOSFET based on the obtained signal flow graphs. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(6): 61–68, 2000
    Electronics and Communications in Japan (Part III Fundamental Electronic Science) 06/2000; 83(6). · 0.14 Impact Factor
  • Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
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    ABSTRACT: The integrator configuration is a filter configuration method involving realization of operational function of each edge by the functional circuits of an integrated circuit based on the signal flow graph with the desired frequency characteristics, and can realize an arbitrary linear time-invariant continuous time system filter. In this paper, a design procedure is proposed for a filter with an integrator configuration in which the frequency deviation is small even if the frequency characteristic of the functional circuit deviates from the ideal one due to the parasitic elements in the circuit. In general, when the integration edge has a feedback edge to return its output to its own input in the signal flow graph, the integration edge and the feedback edge can be realized with ideal lossy integrators on the integrated circuit. Hence, there is a degree of freedom in realization of the integration edge with feedback to itself. In the proposed method, this degree of freedom is fully utilized to reduce the frequency deviation. The equation to evaluate the characteristic deviation by the parasitic elements is derived, and the parameter to express the degree of freedom is determined such that this deviation is reduced. As an application example, a third-order Bessel filter is designed. Its numerical simulation is used for confirming the effectiveness of the proposed method. © 2000 Scripta Technica, Electron Comm Jpn Pt 3, 83(6): 50–60, 2000
    Electronics and Communications in Japan (Part III Fundamental Electronic Science) 06/2000; 83(6):50-60. · 0.14 Impact Factor
  • Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
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    ABSTRACT: This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.
    Analog Integrated Circuits and Signal Processing 01/1998; 16(3):225-238. · 0.55 Impact Factor
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    ABSTRACT: This paper proposes a topology-independent predistortion for filters using integrators. This employs integrators having the same structure, the same-value elements and an electrically controllable unity-gain frequency and compensates for the deviation of frequency characteristics due to excess phase shifts of integrators without knowledge of a filter topology. The effectiveness of the proposed method is demonstrated through SPICE simulations.
    Analog Integrated Circuits and Signal Processing 01/1996; 11(2):119-128. · 0.55 Impact Factor
  • Source
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    ABSTRACT: This paper proposes a design automation for filters using integrators. This is based on a predistortion without knowledge of a filter topology. The predistortion requires an integrator having the same structure, the same-value elements and an electrically controllable unity-gain frequency, and compensates for the deviation of frequency characteristics due to an excess phase shift of an integrator. The effectiveness of the proposed method is demonstrated through SPICE simulations. An algorithm for a filter design automation is also discussed
    Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific; 01/1995

Publication Stats

26 Citations
4.45 Total Impact Points

Institutions

  • 2003–2009
    • Toyohashi University of Technology
      • • Department of Information and Computer Science
      • • Graduate School of Engineering
      Toyohasi, Aichi, Japan
  • 1995–2000
    • Tokyo Institute of Technology
      • Department of Physical Electronics
      Edo, Tōkyō, Japan
  • 1996
    • Toshiba Corporation
      Edo, Tōkyō, Japan