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ABSTRACT: The proposed single-inductor dual-output (SIDO) converter with interleaving energy-conservation mode (IECM) control is designed using 65 nm technology to power the ultra-wide band (UWB) system. The energy-conservation mode (ECM) control generates four different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. Moreover, the IECM control activates the interleaving operation through the current interleaving mechanism to provide large driving capability as well as to reduce the output voltage ripple. As a result, 91% peak efficiency is derived and the output voltage ripple appears notably minimized by 50% using current interleaving at heavy load. The test chip occupies 1.44 mm<sup>2</sup> in 65 nm CMOS and integrates with a three-dimensional (3-D) architecture for inductor integration.
IEEE Journal of Solid-State Circuits 05/2011; · 3.23 Impact Factor
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ABSTRACT: This paper proposes a quadratic differential and integration (QDI) technique for the design of V <sup>2</sup> control buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI technique, which eliminates the use of large ESR in the V <sup>2</sup> control structure, achieves the fast transient response with the small output voltage variation in transient period. Besides, the precise sensing signal is derived from the QDI circuit without the unwilling ESR-related distortion. Moreover, the loop analysis demonstrates that the proposed QDI circuit and the proportional and integral compensator can generate the compensation zero pair to stabilize the system. Experimental results show that the output voltage has small voltage ripple opposite to the conventional V <sup>2</sup> control. In load transient period, the overshoot/undershoot voltage is smaller than 40 mV when output voltage is 2 V, and the transient recovery time inheriting the advantage of V <sup>2</sup> control is shorter than 9 ??s with the load step from 100 to 400 mA and vice versa . The highest full chip power conversion efficiency is about 93%.
IEEE Transactions on Power Electronics 05/2010; · 4.65 Impact Factor
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Yu-Huei Lee,
Yao-Yi Yang,
Ke-Horng Chen,
Ying-Hsi Lin, Shih-Jung Wang,
Kuo-Lin Zheng,
Po-Fung Chen,
Chun-Yu Hsieh,
Yu-Zhou Ke,
Yi-Kuang Chen,
Chen-Chih Huang
J. Solid-State Circuits. 01/2010; 45:2227-2238.
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ABSTRACT: This paper proposes a quadratic differential and integration (QDI) technique for the design of buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI circuit not only further removes the dependence of ESR in the V<sup>2</sup> control but also achieves a fast transient response with small load transient voltage variation. The experimental results show the output voltage can have voltage ripple about 30 mV and recovery time of 20 mus in case of 300 mA load current variation.
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE; 10/2009
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IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings; 01/2009
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ABSTRACT: In this paper, the compensation of internal resistance of the Li-Ion battery is proposed. The requirement of fast and steady charger becomes the most important issue for power management ICs. Refer to the characteristics of the battery, how to charge the battery with adequate current and fasten the time of charging is critical to the devisers. Due to the impedance of battery pack, the energy of charger charged to cell is consumed in it partly. As a result, the efficiency of charger is reduced inevitably. The previous design has proposed a dynamic circuit for reducing time [1]. However the technique demands the external device to compensate the defeat. Thus, this paper extends the period of the CC mode to charge the battery with a faster speed. Owing to the shifting voltage on the reference voltage, the charger can delay the time that the operation mode from CC mode to CV mode. That is a fast-charging charger can be achieved by a large constant current stored in the battery during a long constant current period. Simulation results verify the success of the fast-charging technique due to the internal resistance compensation.
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on; 10/2008
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ABSTRACT: A load dependent proportional-integration (PI) compensation is proposed in this paper for minimizing transient dropout voltage and accelerating the transient response of current mode DC-DC converters. The adaptive compensation resistance and capacitance are used to react to the sudden load variations: At the beginning of load transient response, the adaptive compensation capacitance is decreased to move the compensation pole-zero pair to a higher frequency for achieving fast transient response. At the end of load transient response, the pole-zero pair is moved back to an optimal position for extending the system bandwidth and phase margin based on the instant load condition. Simulation results demonstrate the excellent performance at transient period and steady-state with this proposed fast transient control and adaptive pole-zero compensation. The overshoot/undershoot voltage is smaller than 45mV and transient period is shorter than 15us as load current suddenly changes between 100mA and 500mA.
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on; 06/2008
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International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA; 01/2008
