Chaehyun Jung

Publications (3)2.44 Total impact

• Article: An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications

  Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, J. Cong
  [show abstract] [hide abstract]
  ABSTRACT: A 3-D graphics SoC, with a multi-layer advanced microcontroller bus architecture (AMBA) system, full pipelined hardware 3-D graphics accelerator, and clock/power management is proposed as a 49-mm² die for 180-nm CMOS technology. This system-on-chip (SoC) minimizes power consumption with a clock/power management unit according to its operation mode and applications. The 3-D graphics accelerator has a full pipelined architecture which improves full 3-D graphics performance to 8M polygons/s and consumes 108 mW at 100 MHz and 1.8 V. The LCD bypass mode and power-down mode consume 4.32 mW and 180 uW, respectively. The 3-D graphics accelerator also supports stereoscopic 3-D function with an alternative left-right drawing method and achieves a 59% improvement in 3DG performance compared to previous work.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 09/2011; · 1.22 Impact Factor
• Article: An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications.

  Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong
  IEEE Trans. VLSI Syst. 01/2011; 19:1490-1495.
• Source

  Available from: ucla.edu

  Article: An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications

  Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong
  [show abstract] [hide abstract]
  ABSTRACT: A 3-D graphics SoC, with a multi-layer advanced micro-controller bus architecture (AMBA) system, full pipelined hardware 3-D graphics accelerator, and clock/power management is proposed as a 49-mm die for 180-nm CMOS technology. This system-on-chip (SoC) minimizes power consumption with a clock/power management unit according to its operation mode and applications. The 3-D graphics accelerator has a full pipelined architecture which improves full 3-D graphics performance to 8M polygons/s and consumes 108 mW at 100 MHz and 1.8 V. The LCD bypass mode and power-down mode consume 4.32 mW and 180 uW, respectively. The 3-D graphics accelerator also supports stereoscopic 3-D function with an alternative left-right drawing method and achieves a 59% improvement in 3DG performance compared to previous work. Index Terms—3-D graphics (3DG) accelerator, 3-D display, 3DG system-on-chip (SoC), geometric engine, rendering engine.
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/1490; 19. · 1.22 Impact Factor