Publications (8)0 Total impact
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Article: Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor.
IEEE Trans. Computers. 01/2011; 60:1274-1287. -
Article: Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.
IEEE Trans. Computers. 01/2011; 60:1260-1273. -
Conference Proceeding: Exponent monitoring for low-cost concurrent error detection in FPU control logic.
29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA; 01/2011 -
Conference Proceeding: AVF Analysis Acceleration via Hierarchical Fault Pruning.
16th European Test Symposium (ETS 2011), May 23-27, 2011, Trondheim, Norway; 01/2011 -
Conference Proceeding: Workload-driven selective hardening of control state elements in modern microprocessors.
28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA; 01/2010 -
Conference Proceeding: Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller.
27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA; 01/2009 -
Conference Proceeding: On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors.
2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008; 01/2008 -
Conference Proceeding: Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.
23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA; 01/2008