A. Arbabian

Stanford University, Palo Alto, California, United States

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Publications (14)11.42 Total impact

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    ABSTRACT: High-resolution mm-wave array beamformers have applications in medical imaging, gesture recognition, and navigation. A scalable array architecture for 3D imaging is proposed in which single-element phase coherent transceiver (TRX) chips, with programmable TX pulse delay capability, are mounted on a common board to realize the array. This paper presents the design of the enabling TRX chip: a highly integrated 94 GHz phase-coherent pulsed-radar with on-chip antennas. The TRX achieves 10 GHz of frequency tuning range and 300 ps of contiguous pulse position control, enabling its usage in the large-array imager with time-domain TX beamforming. The TRX is capable of transmitting and receiving pulses down to 36 ps, translating to 30 GHz of bandwidth. Interferometric measurements show the TRX can obtain single-target range resolution better than 375 $mu$m (limited by equipment). Based on delay measurements, the time of arrival rms error would be less than 1.3 ps which, if used in a 3D imaging array, leads to less than 0.36 mm of RMS error in voxel size and position.
    IEEE Journal of Solid-State Circuits 01/2013; 48(4):1055-1071. · 3.06 Impact Factor
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    ABSTRACT: An integrated phase-coherent and pixel-scalable pulsed-radar transceiver with on-chip tapered loop antennas generates programmable pulses down to 36ps using an integrated 94GHz carrier, frequency synthesized and locked to an external reference. A DLL controls the TX pulse position with 2.28ps resolution, which allows the chip to function as a unit element in a timed-array. The receiver also features a >;1.5THz GBW DA as the front-end amplifier, quadrature mixers, and a 26GHz quadrature baseband. Phase coherency allows for ~375μm single-target position resolution by interferometry.
    VLSI Circuits (VLSIC), 2012 Symposium on; 01/2012
  • A. Arbabian, A.M. Niknejad
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    ABSTRACT: A three-stage cascaded distributed amplifier is designed in a 0.13μm SiGe BiCMOS process. By optimizing the amplifier both at the architecture and element level, an extremely large measured gain-bandwidth product in excess of 1.5THz is obtained. The core amplifier consumes 75mA from a 3.3V supply and provides an average gain of 24dB from 15GHz to at least 110GHz (limited by equipment BW). A distributed RF-choke design is employed to provide the bias current to the three cascaded stages. The pass-band gain stays between 23 and 26.5dB.
    Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE; 01/2012
  • Amin Arbabian, Ali M Niknejad
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    ABSTRACT: This paper introduces a silicon-based imaging array for remote measurements of complex permittivity of tissue. Using a coherent pulsed measurement approach, this time-frequency resolved technique recovers the three dimensional mapping of electrical properties of the subject in the microwave/millimeter-wave frequency spectrum. Some of the major challenges in the design of the system are described. Initial measurement results from the prototype high-resolution transmitter fabricated in a 0.13 μm SiGe process are described. The transmitter achieves pulse widths suitable for millimeter-level accuracy imaging.
    Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Conference 08/2011; 2011:505-11.
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    ABSTRACT: This paper reports a fully integrated 90 GHz-carrier pulsed transmitter in 0.13 μm SiGe BiCMOS process for imaging applications. To obtain ultra-short programmable pulses, the transmitter employs a number of novel techniques including hybrid switching and Antentronics. The transmit path includes a quadrature VCO, PA driver, PA and the on-chip folded slot antenna. High speed ECL circuits generate and provide the short pulses in several operating modes. The transmitter achieves a record pulsewidth of 26 ps in the hybrid mode and 33 ps in the independent mode. This translates to >30 GHz of RF BW in the transmitter.
    IEEE Journal of Solid-State Circuits 01/2011; · 3.06 Impact Factor
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    ABSTRACT: A reflective, dual-loop, switching antenna utilizing near-field/far-field energy cancellation is integrated in a 90 GHz pulsed transmitter (TX). The TX features high ON/OFF ratio, good antenna efficiency and PRF up to 3.45 GHz. It achieves TX power of 10 dBm with 18 dB of power tuning. The pulse width is tunable between 46 ps to 310 ps and initial bistatic measurements distinguish 4 reflectors across a 6 cm region signifying progress towards the development of a diagnostic medical imager in silicon.
    01/2011;
  • Maryam Tabesh, Amin Arbabian, Ali M. Niknejad
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    ABSTRACT: Two compact, low-loss, passive reflective type 60GHz phase shifters are presented in a standard 65nm CMOS technology. The designs use lumped-element baluns to implement the hybrid with an insertion loss better than 0.7dB. The first architecture achieves 180 degrees phase shift with an average loss of 6.6dB and area of 0.031mm2. The second phase shifter demonstrates the best reported average loss of 4.5dB with an area of 0.048mm2 while having ~150 degrees of phase shift. Both designs provide more than 10GHz of bandwidth. These are the smallest reported 60GHz phase shifters in silicon.
    2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011; 01/2011
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    ABSTRACT: A fully integrated 90 GHz-carrier pulsed transmitter with on-chip antenna and >30 GHz measured bandwidth is demonstrated in 0.13 ¿m SiGe BiCMOS. By exploring the benefits of hybrid PA/antenna switching and high-performance digital circuitry, the transmitter generates variable-width carrier-modulated pulses with minimum measured pulse width of 35 ps.
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International; 03/2010
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    ABSTRACT: This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10<sup>-11</sup> BER.
    IEEE Journal of Solid-State Circuits 01/2010; · 3.06 Impact Factor
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    A. Arbabian, A.M. Niknejad
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    ABSTRACT: This paper presents the design and measurement of a distributed amplifier (DA) in a standard 90-nm CMOS process. To improve the gain and bandwidth (BW) of the DA, the use of an elevated coplanar waveguide line and also impedance tapering in the synthesized sections are proposed. The effects of elevation and shielding filaments on the impedance, loss, and effective dielectric constant of the transmission line are investigated and accompanied by measurements. A methodology for CMOS DA design is described that can take advantage of the multiple degrees of freedom in terms of device size, topology, and aspect ratio available in these processes. The fabricated tapered cascaded multistage DA achieves a 3-dB BW of 73.5 GHz with a passband gain of 14 dB. This results in a gain-BW product of 370 GHz. The realized 0-dB BW is 83.5 GHz and the input and output matchings stay better than -9 dB up to 77 and 94 GHz, respectively. The chip consumes an area of 1.5 mm times 1.15 mm, while drawing 70 mA from a 1.2-V supply.
    IEEE Transactions on Microwave Theory and Techniques 05/2009; · 2.23 Impact Factor
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    ABSTRACT: This paper presents key design techniques and challenges in implementing one of the first integrated, energy-efficient 60 GHz transceivers including baseband circuitry. The 90 nm CMOS direct-conversion design operates from a 1.2 V supply and has been optimized for 5-to-10 Gb/s QPSK modulation centered at 60 GHz. To achieve power consumption of 170 mW in transmit mode and 138 mW in receive mode, this design leverages co-integration and optimization of mm-wave and mixed-signal baseband circuits.
    IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009
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    A. Arbabian, A.M. Niknejad
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    ABSTRACT: In the presented DA (distributed amplifier) architecture, a feedback mechanism that aims at improving the gain with a minimum reduction in BW is proposed. It is seen that in the band where the distributed effect of the DA is in action, the ratio of the forward to reverse gain is substantial (and depends on the number of stages used). The input and output blocks are connected to this core stage to provide matching and stability This method is different from other techniques that improve gain (e.g., cascade of DAs or matrix amplifier) in that it uses a new internal feedback to fed signals go through one DA twice. The input, core and output DA blocks consist of 4/3/3 gain elements respectively except that the core DA uses series input capacitances at the gates for BW enhancement and biasing purposes. Terminations Z<sub>x</sub> and Z<sub>y</sub> are chosen to minimize undesired reflections. The input and output biases are fed through appropriate bias tees. The lower cutoff of the DA is set at 12 GHz for our application in a wideband mm-wave imaging module. This frequency could be extended to frequencies close to 1 GHz if appropriate AC-coupling capacitors are used.
    Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International; 03/2008
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    A. Arbabian, A.M. Niknejad
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    ABSTRACT: A tapered cascaded multi-stage distributed amplifier (T-CMSDA) has been designed and fabricated in a 90 nm digital CMOS process. The amplifier achieves a 3-dB bandwidth of 73.5 GHz with a pass-band gain of 14 dB. This results in a gain-bandwidth (GBW) product of 370 GHz. The realized zero-dB BW is 83.5 GHz and the input and output matchings stay better than -9 dB up to 77 and 94 GHz, respectively. The chip consumes an area of 1.5 mm by 1.15 mm while drawing 70 mA from a 1.2 V supply.
    Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE; 01/2008
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    ABSTRACT: An internal unilaterization technique for cas-code devices is analyzed and demonstrated in 90 nm CMOS technology. The substrate network of the device has been incorporated in a circuit technique together with an LC tank on the top gate of the cascode structure. The structure is accurately modeled and conditions for unilaterization of the cascode are derived in terms of the the LC tank parameters. An increase in the maximum stable gain from 7.5 dB to 20 dB has been verified in the measurements using this technique.
    Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE; 07/2007