Daniel A. Andersson

Atmel, San Jose, California, United States

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Publications (11)0.28 Total impact

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    ABSTRACT: We present an approach to power integrity analysis that is based on traces resulting from application execution. The first phase of the approach identifies a vector that maximally stresses the power grid, while the second phase entails simulation of the selected vector on an accurate grid model. We show, for an AVR32 32-bit microcontroller, that the vector we identify gives
    01/2011;
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    ABSTRACT: We address two problems of assessing the influence of power- supply variations on timing analysis. We present a method to assign a supply-dependent hold margin; and we describe a method to accurately characterize logic gates for the sen- sitivity of delay on supply-voltage variations. We use a com- mercial microcontroller as a design example.
    Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010; 01/2010
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    ABSTRACT: Conventional IR drop analysis suggests that on-chip inductive effects can be neglected when estimating supply voltage drops. We present a supply voltage drop analysis for a commercial 32-bit application processor. Our power grid model uses a backbone RL extracted netlist of the processor's power grid, complemented with capacitances from the processor design and a current signature defined by the worst-case switching test vector, located in the power-up sequence of the processor. Our circuit simulations show that on-chip self inductance makes the actual supply voltage drop deviate by more than 55% and 25% from the ~6% and ~8% drop, respectively, of nominal supply voltage that a conventional IR power grid model yields.
    Signal Propagation on Interconnects, 2009. SPI '09. IEEE Workshop on; 06/2009
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    ABSTRACT: We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.
    01/2009;
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    ABSTRACT: The authors present a new method to find low-complexity time-domain interconnect models that obey a certain specified accuracy in relation to the true waveform. The method rests on an characterisation flow that considers the whole interconnect environment, including driver and receiver. Furthermore, as output the method defines simple rules for appropriate model segment type, RC or RLC and minimal number of model segments. The authors show the application of the method by deriving segment-selection rules for one case, using a particular interconnect, driver, receiver and discrepancy constraint on model against true waveform. In a comparison with a reduced-order modelling technique, the models obtained from the method show good correlation to Lanczos-process-based Krylov subspaces.
    IET Computers & Digital Techniques 08/2008; · 0.28 Impact Factor
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    ABSTRACT: We have investigated the interaction between power delivery and substrate coupling in terms of noise. From our results, we identify that an increased density of substrate contacts does not to any significance decrease noise on the power supply lines. However, the current injected into the substrate is highly dependent on higher-level grid/package inductance and substrate contact density. We have derived statistically that substrate noise variations could be related to these two design parameters to 69.75%. Based on linear fitting, a model that describes the injected current as function of substrate contact density and power delivery inductance is developed.
    Quality Electronic Design, International Symposium on. 03/2008;
  • Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
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    ABSTRACT: We analyze the correlation between different parameters of the on-chip power distribution grid and their impact on noise. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. We derive the correlation between design variables and noise from an analysis of 300 different grids in a 65-nm process technology, and manage to find the impact that a change in power grid design variables will have on noise. The results from this analysis can be used as guidelines when designing a robust power distribution grid.
    9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA; 01/2008
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    ABSTRACT: We present a systematic way of performing sensitivity analysis on on-chip power distribution grids. By using factor analysis we are able to uncover correlations between power grid design variables and power supply noise. From our analysis of 300 different grids in a 65-nm process, we can identify which power grid design variables have both high correlation to and high impact on noise; the most important one being supply rail width.
    Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on; 06/2007
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    ABSTRACT: We present a new method to find minimal-complexity interconnect models that obey a certain specified accuracy in relation to the true waveform. The method can be described as an interconnect characterization flow that defines simple rules for finding the minimal number of segments and required segment type, RC or RLC, by regarding interconnect resistance, driver source resistance, interconnect characteristic impedance and load capacitance. To show the application of the method, segment selection rules are derived for a case with a waveform discrepancy constraint of 5%
    Norchip Conference, 2006. 24th; 12/2006
  • Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
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    ABSTRACT: Since the skin effect will increase the propagation delay in an interconnect, it will also affect how to optimally select the number and size of the buffers. Failing to include the skin effect during buffer design may result in as much as 35% extra delay compared to the optimal repeater chain. We present a new method with closed-form expressions for repeater insertion where we take into account the skin effect and also the relationship between interconnect resistance, capacitance and inductance that are determined from the geometrical parameters. We also investigate the skin-effect influence on power dissipation for an optimally designed repeater chain, and find that the increase is at most 10% of the dynamic power dissipation.
    Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005; 01/2005
  • Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors
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    ABSTRACT: We investigate the influence of skin effect on the propagation delays of on-chip interconnects. For long wires, designed in the LC regime, on the top metal layer in a contemporary process, we find that the skin effect causes an extra delay by 10%. The impact of the skin effect on delay is furthermore rapidly increasing with increased interconnect width.
    Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings; 01/2004

Publication Stats

9 Citations
0.28 Total Impact Points

Institutions

  • 2009
    • Atmel
      San Jose, California, United States
  • 2005–2008
    • Chalmers University of Technology
      • Department of Computer Science and Engineering
      Göteborg, Vaestra Goetaland, Sweden