Shyh-Jong Chung

National Chiao Tung University, Hsinchu, Taiwan, Taiwan

Are you Shyh-Jong Chung?

Claim your profile

Publications (4)5.42 Total impact

  • Article: Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection
    [show abstract] [hide abstract]
    ABSTRACT: Two 3-5-GHz low-power ultra-wideband (UWB) low-noise amplifiers (LNAs) with out-band rejection function using 0.18- ??m CMOS technology are presented. Due to the Federal Communications Commission's stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile communications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band properties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.
    IEEE Transactions on Microwave Theory and Techniques 03/2010; · 1.85 Impact Factor
  • Article: A 2.45/5.2 GHz Image Rejection Mixer With New Dual-Band Active Notch Filter
    [show abstract] [hide abstract]
    ABSTRACT: A 2.45/5.2 GHz dual-band Gilbert downconversion mixer with image rejection function is presented, which is implemented using the 0.18 mum CMOS technology. The proposed differential dual-band image rejection circuitry is employed for the 2.45/5.2 GHz WLAN application to effectively diminish the DC power consumption and complexity of circuit design compared to the traditional Hartley or Weaver architectures. Moreover, the cross-connected pair consisted of NMOS and PMOS transistors in the proposed notch filter will further ameliorate the image rejection capability. The IC prototype achieves conversion gain of 10.5/11 dB, IIP3 of -4.9/-5.2 dBm for RF = 2.45/5.2 GHz and IF = 500 MHz while the image rejection ratio is better than 36/45 dB in the whole operation bandwidth.
    IEEE Microwave and Wireless Components Letters 12/2009; · 1.72 Impact Factor
  • Article: An Ultra-Wideband High-Linearity CMOS Mixer With New Wideband Active Baluns
    [show abstract] [hide abstract]
    ABSTRACT: A 2-11-GHz high linearity CMOS down-conversion mixer with wideband active baluns using 0.18-mum CMOS technology is demonstrated in this paper. The mixer employs a folded cascode Gilbert cell topology and on-chip broadband active baluns. The folded cascode approach is adopted to increase the output swing, and the linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The proposed configuration shows the highest IIP<sub>3</sub> and IP<sub>1</sub> <sub>dB</sub>, and exhibits more compact size than most published studies. A broadband active balun is used to generate wideband differential signals, together with the derivation of a closed-form expression for the phase imbalance. This single-ended wideband mixer has the conversion gain of 6.9plusmn1.5 dB, input 1-dB compression point (IP<sub>1</sub> <sub>dB</sub>) of - 3.5 dBm, single-sideband noise figure of 15.5 dB, and third-order input intercept point (IIP<sub>3</sub>) of 6.5 dBm under the power consumption of 25.7 mW from a 1.8-V power supply. The chip area is 0.85 x 0.57 mm<sup>2</sup>.
    IEEE Transactions on Microwave Theory and Techniques 10/2009; · 1.85 Impact Factor
  • Conference Proceeding: A Wideband CMOS Mixer with Feedforward Compensated Differential Transconductor
    [show abstract] [hide abstract]
    ABSTRACT: A 2.4 to 10.7 GHz wideband mixer for multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) applications is designed using a TSMC 0.18mum CMOS technology. The designed mixer uses a LC folded cascode structure and a feedforward compensated high-linearity differential transconductor to improve the linearity. The measured results reveal that the proposed mixer achieves power conversion gain of 3.3 plusmn 1.5 dB, third-order input intercept point (IIP3) of 6.9 dBm, and input 1-dB compression point (P-1dB) of -2.8 dBm in the power consumption of 14.4mW from a 1.8V power supply. The chip area is 0.70 times 0.58 mm<sup>2</sup>.
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on; 06/2007