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Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009; 01/2009
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Toshihiro Hattori,
Takahiro Irita,
Masayuki Ito,
Eiji Yamamoto,
Hisashi Kato,
Go Sado,
Tetsuhiro Yamada,
Kunihiko Nishiyama,
Hiroshi Yagi, Takao Koike, [......],
Shinichi Yoshioka,
Toshifumi Ishii,
Yusuke Kanno,
Hiroyuki Mizuno,
Tetsuya Yamada,
Naohiko Irie,
Reiko Tsuchihashi,
Nobuto Arai,
Tomohiro Akiyama,
Koji Ohno
Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006; 01/2006
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ABSTRACT: A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.
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Toshihiro Hattori,
Takahiro Irita,
Masayuki Ito,
Eiji Yamamoto,
Hisashi Kato,
Go Sado,
Tetsuhiro Yamada,
Kunihiko Nishiyama,
Hiroshi Yagi, Takao Koike, [......],
Shinichi Yoshioka,
Toshifumi Ishii,
Yusuke Kanno,
Hiroyuki Mizuno,
Tetsuya Yamada,
Naohiko Irie,
Reiko Tsuchihashi,
Nobuto Arai,
Tomohiro Akiyama,
Koji Ohno
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ABSTRACT: A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU's that is baseband processor, application processor, and multi-media processor. In the "waiting for calling" mode of the mobile handsets, application processor and multi-media processor part can be power-off. This chip can power off these power domains although the some of baseband parts are actively operating.. Many new techniques for multiple power domains in the chip are described.This paper describes the output of two projects. (1) Fundamental circuits research on hierarchical power domain = joint research by Hitachi, Ltd. and Renesas Technology Corp.[4] (2) LSI design for one chip mobile processor = joint development by NTT DoCoMo Inc. and Renesas Technology Corp.[5].
