C. Stroud

Auburn University, Auburn, AL, United States

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Publications (135)27.55 Total impact

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    ABSTRACT: This paper proposes selective spectrum analysis (SSA) technique that uses two multiplier/accumulators to estimate the spectrum. It requires much less area overhead than Fast Fourier Transform (FFT) and offers better performance in terms of area overhead, dynamic range, and accuracy than analog spectrum estimation techniques. As a result, SSA is a good output response analyzer (ORA) implementation for mixed-signal Built-In Self-Test (BIST). The SSA technique downconverts the device under test output at the interested frequency to dc by multiplication and filters out the undesired ac components through accumulation. But the ac components cannot be completely removed and introduce calculation errors. While these errors can be minimized by controlling the accumulation time, the rate of convergence is low such that long test time is required to achieve reasonable accuracy. An alternate approach is to choose integer multiple periods (IMPs) of the frequency under analysis to stop the accumulation. Performance of the SSA-based ORA is analyzed in a systematic way and it is shown that the proposed IMP circuits can further improve the efficiency of the ORA in terms of test time, area overhead, and measurement accuracy. Experimental results are presented for simulation as well as implementations of the SSA technique in field-programmable gate arrays and standard cell application specific integrated circuits.
    IEEE Transactions on Industrial Electronics 11/2011; · 6.50 Impact Factor
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    ABSTRACT: This paper introduces and details a Built-In Self-Test (BIST) approach designed for the embedded Block Random Access Memories (BRAMs) found within Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). The BIST is designed to test the BRAMs in all configurable modes of operation including single-port, dual-port, first-in first-out (FIFO), first-in first-out with error correcting code (FIFOECC), and error correcting code (ECC) modes. The BIST architecture and implementation in actual Virtex-5 FPGAs will be discussed along with fault detection and timing analysis data taken from those implementations.
    System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on; 04/2011
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    M.A. Lusco, J.L. Dailey, C.E. Stroud
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    ABSTRACT: This paper describes a Built-In Self-Test (BIST) approach designed to verify the integrity of the embedded multiplier cores in Altera Cyclone II Field Programmable Gate Arrays (FPGAs). This approach uses an architecture independent test algorithm implemented with parameterized VHDL to support all FPGAs in the Cyclone II family. The BIST is capable of detecting faults within all of the multiplier's modes of operation in three downloads and can identify the location of faulty multiplier(s).
    System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on; 04/2011
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    C.E. Stroud, N.S. Da Cunha
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    ABSTRACT: We present a modified Built-In Self-Test (BIST) approach for programmable clock buffers in Xilinx Virtex-4, Virtex-5, and Virtex-6 Field Programmable Gate Arrays (FPGAs). While seemingly trivial, these critical clock buffer modules present interesting testing challenges as will be described in this paper. A timing problem was found in the previously reported BIST approach for the clock buffers, where the simultaneous switching of inputs to the clock buffers can produce different responses which result in a BIST failure indications in a fault-free device. In addition, the previous approach used normal signal routing resources to route the clock signal to BIST circuitry instead of dedicated clock routing resources, and this may have contributed to the timing problem. We present and discuss modifications that solve the timing problem as well as their impact on the maximum BIST clock frequency and total test time based on implementation and execution in actual Virtex-4 and Virtex-5 FPGAs.
    System Theory (SSST), 2011 IEEE 43rd Southeastern Symposium on; 04/2011
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    ABSTRACT: The paper presents the design of a wideband low noise amplifier (LNA) with self-healing technology that can simultaneously adjust both the peak gain frequency and the input matching frequency to the operating frequency. The gain of proposed LNA is also adjustable. The proposed self-healing LNA is implemented in a 0.13um SiGe BiCMOS technology. The operating frequency of the proposed LNA can be adjusted from 4.5GHz to 7.8GHz. The LNA achieves typical gain of 19dB with 14dB continuous tuning range. The measured input matching is below -12dB over the entire frequency band. The measured noise figure of the LNA is 4.2dB at 7.8GHz, and the output 1dB compression point is -9dBm. The LNA dissipates 52mW power.
    Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2011 IEEE; 01/2011
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    ABSTRACT: We describe a Built-in Self-Test (BIST) approach that was developed for the programmable Input/Output (I/O) buffers in Field Programmable Gate Arrays (FPGAs). The approach is unique when compared with previous work because the I/O buffers are tested separately from the other programmable logic in the I/O cells. The capabilities and limitations of system-level use of this I/O buffer BIST are discussed in conjunction with experimental results from the implementation and actual use of the approach in systems.
    IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the; 04/2010
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    M.D. Pulukuri, G.J. Starr, C.E. Stroud
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    ABSTRACT: We evaluate some of the previously proposed test algorithms and approaches for various types of multipliers. We present methods to effectively test multipliers independent of their architecture and to achieve greater than 99% single stuck-at gate-level fault coverage with a simple 8-bit or 9-bit binary up-counter and some multiplexers. Finally, we discuss testing the multipliers present in most current Field Programmable Gate Arrays (FGPAs).
    IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the; 04/2010
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    M.A. Lusco, C.E. Stroud
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    ABSTRACT: A Processor SIMulator (PSIM) for a basic stored program computer architecture is described which graphically displays the architecture while showing the detailed operation on a per clock cycle basis. The instruction set consists of twenty-five instructions that can be combined to execute many complex capabilities including conditional branching. The current version of PSIM includes an assembler for compiling assembly language programs to machine language code, the ability to display values in various formats including decimal and hexadecimal, and the ability to display and write to a file the contents of the program memory at any point in the simulation.
    IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the; 04/2010
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    B.F. Dutton, C.E. Stroud
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    ABSTRACT: This paper presents the results of a case study which investigates the use of an embedded soft-core processor to perform Built-In Self-Test (BIST) of the logic resources in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). We show that the approach reduces the complexity of an external BIST controller and the number of external reconfigurations, making it particularly appealing for in-system testing of high-reliability and fault-tolerant systems with FPGAs. However, the overall test time is not improved due to an increase in the size of the required configuration files as a consequence of the inclusion of the soft-core embedded processor logic, whose relative irregularity results in less effective compression of configuration data files.
    System Theory (SSST), 2010 42nd Southeastern Symposium on; 04/2010
  • Laung-Terng Wang, Charles E. Stroud
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    ABSTRACT: Very-large-scale integration (VLSI) testing encompasses all spectrums of test methods and structures embedded in a system-on-chip (SOC) to ensure the quality of manufactured devices during manufacturing test. The test methods typically include fault simulation and test generation, so that quality test patterns can be supplied to each device. The test structures often employ specific design for testability (DFT) techniques, such as scan design and built-in self-test (BIST), to test the digital logic portions of the device. To provide readers with basic understanding of the most recent DFT advances in logic testing, memory testing, and SOC testing for low-power device applications, this chapter covers a number of fundamental test methods and DFT structures to facilitate testing of modern SOC circuits. These methods and structures are required to improve the product quality and reduce the defect level and test cost of the manufactured devices, while at the same time simplifying the test, debug, and diagnosis tasks.
    03/2010: pages 1-29;
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    Charles E. Stroud, Bradley F. Dutton
    Proceedings of the 2010 International Conference on Embedded Systems & Applications, ESA 2010, July 12-15, 2010, Las Vegas Nevada, USA; 01/2010
  • Bradley F. Dutton, Charles E. Stroud
    I. J. Comput. Appl. 01/2010; 17:59-69.
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    B.F. Dutton, C.E. Stroud
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    ABSTRACT: This paper presents the first implementation of built-in self-test (BIST) of field programmable gate arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under test, control of BIST execution, retrieval of BIST results, and fault diagnosis. The approach was implemented in Xilinx Virtex-5 FPGAs but is applicable to any FPGA that contains an internal configuration memory access port.
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on; 11/2009
  • F. F. Dai, C. E. Stroud, J. B. Zhang
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    ABSTRACT: This special section includes nine papers in the areas of radiofrequency identification (RFID) design, application, and test, providing a comprehensive look at the unique issues, challenges, and capabilities of this relatively recent technological advance.
    IEEE Transactions on Industrial Electronics 08/2009; · 6.50 Impact Factor
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    M.D. Pulukuri, C.E. Stroud
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    ABSTRACT: We present a Built-In Self-Test (BIST) approach for testing and diagnosing the embedded digital signal processors (DSPs) in Xilinx Virtex-4 series Field Programmable Gate Arrays (FPGAs). The BIST architecture and configurations needed to test these programmable DSPs in all of their modes of operation are presented along with fault injection and timing analysis of the BIST configurations.
    System Theory, 2009. SSST 2009. 41st Southeastern Symposium on; 04/2009
  • Wiley Encyclopedia of Computer Science and Engineering, 03/2009; , ISBN: 9780470050118
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    Bradley F. Dutton, Charles E. Stroud
    Proceedings of the ISCA 24th International Conference on Computers and Their Applications, CATA 2009, April 8-10, 2009, Holiday Inn Downtown-Superdome, New Orleans, Louisiana, USA; 01/2009
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    Proceedings of the 2009 International Conference on Embedded Systems & Applications, ESA 2009, July 13-16, 2009, Las Vegas Nevada, USA; 01/2009
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    Jia Yao, Bobby Dixon, Charles Stroud, Victor Nelson
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    ABSTRACT: We describe the implementation of a crosscoupled parity Built-In Self-Test (BIST) approach for the global routing resources in Field Programmable Gate Arrays (FPGAs). The BIST approach facilitates systemlevel testing of the FPGA global routing resources prior to configuring the intended system function for high reliability/availability systems. We discuss the application of the BIST approach to the global routing resources in Xilinx Virtex-4 FPGAs including experimental results of implementations in actual devices.
    Southeastern Symposium on System Theory. 01/2009;
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    Mary D. Pulukuri, Charles E. Stroud
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    ABSTRACT: We evaluate some previously proposed test approa ches for various types of adders in an attempt to find an architecture-independent algo rithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self -Test (BIST) approach provides the highest fault coverage for most types of adders and, equall y important, it is simple to implement.
    Journal of Electronic Testing 01/2009; 25:343-346. · 0.45 Impact Factor

Publication Stats

2k Citations
27.55 Total Impact Points

Institutions

  • 2003–2011
    • Auburn University
      • Department of Electrical & Computer Engineering
      Auburn, AL, United States
  • 2007
    • Wright State University
      • Department of Electrical Engineering
      Dayton, OH, United States
  • 2001–2003
    • University of North Carolina at Charlotte
      • Department of Electrical & Computer Engineering
      Charlotte, NC, United States
  • 1993–2001
    • University of Kentucky
      • Department of Electrical and Computer Engineering
      Lexington, KY, United States