Jian Chen

Hangzhou University, Hang-hsien, Zhejiang Sheng, China

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Publications (7)0 Total impact

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    ABSTRACT: The reconfigurable devices such as CPLD and FPGA become more popular for its great potential on accelerating applications. They are widely used as an application-specified hardware accelerator. Many run-time reconfigurable platforms are introduced such as the Intel® QuickAssist Technology. However, it’s time consuming to design a hardware accelerator while the performance is hard to determine because of the extra overheads it involved. In order to estimate the efficiency of the accelerator, a theoretical analysis of such platforms was done in our paper. Three factors which impact the performance of the accelerator were concluded as well: speed up ratio, reconfiguration overhead and communication overhead. Furthermore, a performance model was established and an experiment on bzip2 was done to verify the model. The results showed that the model’s estimation is very close to the real world and the average error on the efficiency’s threshold is less than 5%.
    Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings; 01/2009
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    ABSTRACT: As the handsets integrated the J2ME environment is increasing in recent time. After PhoneME which is one implementation of the J2ME had become an open project, transplanting it to many different platforms become a hotspot for some time. There are some implementations for the online debugging between the PC and specific embedded device. But there isn't a well-designed architecture for the debugging processes between the PC and the mobile phone, there just some assistance tools for co-debug. As the mobile phone industry developing, there are many smart phones with affluent hardware resource. This makes the co-debug between PC and smart mobile phone become possible. In this paper, we present a debug framework for the Java application development platform across the PC and mobile phone. With this framework, we can develop the MIDlets for specific embedded device more convenient.
    International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, ScalCom-EmbeddedCom 2009, Dalian, China, September 25-27, 2009; 01/2009
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    ABSTRACT: The multi-core has become inevitable and on-chip communications network to replace the traditional structure of the shared bus architecture has become the trend of the computer science development. Obverse that a general router in mesh NoC have four access interfaces, at the border of the chip does not take full advantage of these interfaces, that is say, only router in middle of chip fully utilized. Hence, we have the main peripheral controllers are directly connected to the router of these unutilized interfaces, means border unutilized routing interface. Then the paper proposes an architecture that the NoC mesh network is divided into several virtual regions which take advantage of applications characteristics to adapt the IO external communication requirements and of the applications self internal communication patterns. Suit for parallel programming model, high I/O demanding system and utilize the existing hardware resources, our scheme is promising.
    International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, ScalCom-EmbeddedCom 2009, Dalian, China, September 25-27, 2009; 01/2009
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    ABSTRACT: Scratchpad memory (SPM) is software-controlled on-chip memory with shorter access time and lower power consumption compared with cache. SPM is used increasingly widespread to meet the strict requirements on performance, power consumption and design cost of the embedded systems. This paper presents an efficient SPM management based on multi-thread for multiprocessor system on chip (MPSoC) architecture, which is the popular in embedded processors. The proposed mechanism is composed of: (1) processor core groups; (2) SPM primitives; (3) SPM based multi-thread scheduling. The experimental results show that the proposed mechanism can improve the performance of the system with lower power consumption.
    International Conference on Scalable Computing and Communications / Eighth International Conference on Embedded Computing, ScalCom-EmbeddedCom 2009, Dalian, China, September 25-27, 2009; 01/2009
  • Conference Paper: SPM-Based Boot Loader
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    ABSTRACT: Nowadays, boot loader becomes more and more important in system, especially the embedded systems which are widely used in different field. Also, many complicated functions have been and will be integrated into boot loader. However, traditional boot loader in embedded system is located in flash or memory which is much slow. The system-on-a-chip technology provides the scratch-pad memory (SPM), which is small, isolated and located on a single chip. It is possible to make use of the SPM in boot loader to boot a system much faster. In this paper, we present a new way of loading process of operating system. Most of boot loaderpsilas work is assigned to another loader- SPMOS loader. It locates in SPM, which provides much faster access than SDRAM and FLASH. The experiment results show that the whole loading process based on SPMOS is fast and efficient.
    Embedded Software and Systems Symposia, 2008. ICESS Symposia '08. International Conference on; 08/2008
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    ABSTRACT: With the development of embedded technology, smart home has been widely used to practice field. Due to the characteristics of cross-platform and faster development life cycle, Java becomes one of the most important language in the mobile application development. From the overall view of application development, this paper describes a Java-based application development platform (JADP) for the mobile system. Our platform¿s features include flexible remote debugger, rich APIs and service components, efficient deploy tool etc. Mobile device applications developers can now easily develop, optimize, deploy and verify their applications with our Java development platform.
    The Second International Conference on Future Generation Communication and Networking, FGCN 2008, Volume 2, Workshops, Hainan Island, China, December 13-15, 2008; 01/2008
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    ABSTRACT: This paper proposes a hardware approach to improving information retrieval efficiency on the vector space model. We design a heterogeneous multicore system, within which auxiliary retrieval-oriented intellectual properties (IP) cores perform term counting as basic operations. Moreover, a memory system is also designed to supply data efficiently. Since term counting is a highly frequent operation in information retrieval, we hope the overall efficiency will improve significantly as a result of hardware implementation of term counting. The experiment shows that our system has a speedup of 3 to 7 for different input data. We have also analyzed the influence of data patterns on performance.
    Fifth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2008, 18-20 October 2008, Jinan, Shandong, China, Proceedings, Volume 5; 01/2008