Tatsuya Saito

Publications (6)0 Total impact

• Conference Proceeding: 10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.

  Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura
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  ABSTRACT: The authors presents a 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX. This gearbox LSI implemented in 65nm CMOS decreases power dissipation by 75% compared to that of a conventional LSI.
  IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
• Article: A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.

  Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura
  J. Solid-State Circuits. 01/2011; 46:3101-3112.
• Conference Proceeding: A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS.

  Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
  IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010
• Article: A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.

  Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito
  J. Solid-State Circuits. 01/2010; 45:2838-2849.
• Conference Proceeding: A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS.

  Takashi Takemoto, Fumio Yuki, Hiroki Yamashita, Shinji Tsuji, Tatsuya Saito, Shinji Nishimura
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  ABSTRACT: A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch and demonstrates the transimpedance bandwidth products per DC power of 952.1 GHzΩ/mW and crosstalk of less than -17 dB. The sensitivity at bit error rate (BER) of less than 10^-12 was measured to be the optical input power of -7.4 dBm for multi-channel operation at the data rate of 25 Gb/s, and also demonstrates only 0.8 dB power penalty.
  IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings; 01/2010
• Conference Proceeding: 10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1

  Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Tatsuya Saito
  IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009; 01/2009