Sang-Hyup Kwak

Publications (4)3.23 Total impact

• Article: A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

  Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, [......], Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
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  ABSTRACT: This paper describes a 1 Gbit GDDR5 SDRAM with enhanced bank access flexibility for efficient data transfer in 7 Gb/s per pin IO bandwidth. The enhanced flexibility is achieved by elimination of bank group restriction and reduction of bank to bank active time to 2.5 ns. The effectiveness of these key features is verified by system model simulation including memory and its controller. To realize the enhanced bank access flexibility, this DRAM employs the following techniques: skewed control logic, PVT variation compensated IO sense amplifier with auto calibration by replica impedance monitor, FIFO based BLSA enable signal generator, low latency VPP generator and active jitter canceller. This GDDR5 SDRAM was fabricated in 50 nm standard DRAM process in 61.6 die area and operates with 1.5 V power supply.
  IEEE Journal of Solid-State Circuits 02/2011; · 3.23 Impact Factor
• Conference Proceeding: A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.

  Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim, Sang-Hyup Kwak, Ho-Seok Seol, Chang-Ho Shin, Min-Sang Park, [......], Sun-Young Park, Yong-Jae Shin, Gil-Shin Moon, Cheol-Goo Park, Woo-Seop Kim, Hyang-Ja Yang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
  IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011
• Conference Proceeding: A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

  Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Sang-Hyup Kwak, Dong-Min Kim, Dae-Hyun Kim, Young-Sik Kim, Yoo-Seok Yang, Su-Yeon Doo, Jin-Il Lee, Sam-Young Bang, Sun-Young Park, Ki-Woong Yeom, Jae-Young Lee, Hwanwook Park, Woo-Seop Kim, Hyang-Ja Yang, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
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  ABSTRACT: A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40 nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670 fs RMS. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to the integrating DFE. Moreover, on-chip de-emphasis circuit in TX multiplexer reduces ISI of both on and off chip.
  VLSI Circuits (VLSIC), 2010 IEEE Symposium on; 07/2010
• Conference Proceeding: A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

  Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, [......], Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun
  IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010; 01/2010