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ABSTRACT: A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm<sup>2</sup> and 0.06 mm<sup>2</sup> die area, respectively. The dual-band transceiver achieves error-free operation (BER <; 10<sup>-15</sup> ) with 2<sup>23</sup>- 1 PRBS at 8.4 Gb/s over a distance of 10 cm.
IEEE Journal of Solid-State Circuits 02/2012; · 3.23 Impact Factor
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J. Solid-State Circuits. 01/2012; 47:117-130.
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ABSTRACT: In summary, we have designed and fabricated a DBI for mobile DRAM I/O interface in 65nm CMOS to obtain an aggregate data throughput of 8.4Gb/s and 10Gb/s on FR4 and Roger test boards, respectively, with power consumptions of 21 mW and 25mW. The BERs for both test boards are measured as <;1x10<sup>-15</sup> by using 2<sup>23</sup>-1 PRBS from the Agilent-70843C.
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International; 03/2011
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IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011; 01/2011