E. Morifuji

Toshiba Corporation, Edo, Tōkyō, Japan

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Publications (67)35.42 Total impact

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    ABSTRACT: We have developed a compact model which deals with MOSFET characteristic variations arising from design layout dependences. It treats many stress related variations and their interactions that are especially important in 45 nm technology node. It is demonstrated that the model can predict MOSFET characteristics used in standard cells with high accuracy.
    Electron Devices Meeting (IEDM), 2009 IEEE International; 01/2010
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    ABSTRACT: Layout dependences for stress-enhanced MOSFETs including contact positioning, the second neighboring poly effect, and bent diffusion are modeled in 45-nm CMOS logic technology. It is found that the sensitivity of contact position in the channel direction is larger for PMOS with a higher stress liner than for NMOS. The effect of contact positions is modeled by using the distance of contact to gate ( x ) and the number of contacts ( N ). In terms of the gate-space effect, it is concluded that, in addition to the neighboring gates, second neighboring gates affect the channel stress. The effect of bent-shape diffusion is analyzed for NMOS and PMOS. For NMOS, the channel profile is affected by the bent shape. This can be described by the change of V <sub>th</sub>. For PMOS, the channel stress is modulated by the bent diffusion. The stress effect in bent-shape diffusion for PMOS is modeled with three geometrical parameters. The compact model is applied to the characterization of actual 45-nm cell libraries. It is confirmed that, with the constructed models and design flow, a saturation current ( I <sub>dsat</sub>) change of -12%-14% is removed from the uncertain margin in 45-nm corner libraries.
    IEEE Transactions on Electron Devices 10/2009; · 2.06 Impact Factor
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    ABSTRACT: Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm<sup>2</sup> is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum<sup>2</sup> SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International; 01/2009
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    ABSTRACT: Optimum methodology of scaling for RF complementary metal-oxide-semiconductor (CMOS) has been studied by investigating cutoff frequency ( fT), maximum oscillation frequency ( fmax), RF noise, and linearity with simulations and experiments. In the case of MOS field effect transistors (MOSFETs) with multi-finger structure, fmax and noise figure show trade-off between gate resistance and gate-bulk capacitance because of the existence of gate area for contact. By optimizing finger length for each technology, high fmax and low minimum noise figure are realized with little sacrifice of fT. In terms of the linearity, optimized gate width scaling is important. Stress enhancement technique is confirmed to be beneficial also in RF performance because of the enhancement of mobility which results in improvement of fT and other RF characteristics. It should be concluded that the improvement of RF characteristics is expected with scaling down the devices by adding gate width and finger length as the significant scaling parameters.
    Japanese Journal of Applied Physics 01/2009; 48. · 1.07 Impact Factor
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    ABSTRACT: The effect of stress memorization technique (SMT) on performance of transistors and power reduction is intensively studied. A 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously by choosing the appropriate stressor film with a large stress change by spike rapid thermal annealing (RTA). Stress distribution in the channel region for SMT is confirmed to be uniform; hence, the layout dependence is minimized and the performance is maximized in aggressively scaled complementary metal-oxide-semiconductor (CMOS) with dense gate pitch rule (190 nm) in 45 nm technology node.
    Japanese Journal of Applied Physics 01/2009; 48. · 1.07 Impact Factor
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    ABSTRACT: Gate density is ultimately increased to 2100 kGates/mm<sup>2</sup> by pushing the critical design rules without increasing the circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled for the first time. With the constructed design flow, gate length change of -2.8% to +3.6% and Idsat change of -10% to +14% are removed from uncertain margin in 45 nm corner libraries.
    VLSI Technology, 2008 Symposium on; 07/2008
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    ABSTRACT: We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally optimized total power and the corresponding temperature as a function of delay for a given set of transistors (bulk, double-gate FET, fully depleted SOI, and partially depleted SOI) at future technology nodes. When SPICE models are not necessarily available and simple device models are highly inadequate because of complex 2D device effects, these derived power/temperature versus delay curves serve as a comprehensive standard to compare any two transistors for future technology-node device selections. Because the power optimization is global (over various transistor parameters and includes leakage as well as dynamic power) and is self-consistently coupled to electro-thermal models, the methodology provides the optimum operational supply voltage (V<sub>dd</sub>) and the device parameters (body thickness, equivalent oxide thickness, and gate metal work function) for future transistors targeting 45-nm technology node. Furthermore, it can be used to provide insight into advance nodes, device-specific hot-spot problems, multiple V<sub>t</sub>, V<sub>dd</sub> design for different functional blocks, transistor design, and evaluating the efficacy of novel thermal solutions such as superior thermal conductivity and subambient cooling.
    IEEE Transactions on Electron Devices 08/2007; · 2.06 Impact Factor
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    ABSTRACT: We have developed a self-consistent, electro-thermally coupled, total power, (includes dynamic, DP, and static leakage power, SDL) optimization methodology for future transistors. It calculates the best power-delay tradeoff curve, and the corresponding self-consistent, temperature-delay curves for a given transistor from its current-voltage characteristics. The methodology, by serving as a comprehensive comparison standard for different future transistor options, presents a unique and powerful tool for suitable device selection at future nodes, where no SPICE models are available. In addition, in this work, we also use the methodology to provide insight into the (1) optimum transistor design and operational parameters for minimum P<sub>tot</sub>, (2) device-specific hot spot problems, (3) multi-Vt design for different functional blocks, and (4) the efficacy of novel thermal solutions (superior thermal conductivity, sub-ambient cooling). We choose an 18nm gate length (Lg) double gate FET (DGFET) to illustrate the methodology.
    Device Research Conference, 2007 65th Annual; 07/2007
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    ABSTRACT: The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large stress change by spike RTA. 30% mobility enhancement and 60% reduction of gate leakage have been achieved simultaneously. Stress distribution in channel region for SMT is confirmed to be uniform, hence layout dependency is minimized and performance is maximized in aggressively scaled CMOS with dense gate pitch rule (190 nm) in 45 nm technology node.
    VLSI Technology, 2007 IEEE Symposium on; 07/2007
  • E. Morifuji, D. Patil, M. Horowitz, Y. Nishi
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    ABSTRACT: With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these tradeoffs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. The use of analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (V<sub>dd</sub>) nor the gate length (L<sub>g</sub>) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (L<sub>g</sub>) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. The suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area
    IEEE Transactions on Electron Devices 05/2007; · 2.06 Impact Factor
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    ABSTRACT: The authors show new guidelines for V<sub>dd</sub> and threshold voltage (V<sub>th</sub>) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V<sub>dd</sub> is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V<sub>dd</sub>s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V<sub>dd</sub> and V<sub>th</sub> are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V<sub>dd</sub> should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V<sub>dd</sub> for SRAM operation. In high-density SRAM, low V<sub>th</sub> causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V<sub>th</sub> should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V<sub>dd</sub> for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.
    IEEE Transactions on Electron Devices 07/2006; · 2.06 Impact Factor
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    ABSTRACT: In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM (CMOS5L) is reported. It offers wide range of Vth lineup and very low gate leakage as 0.06A/cm<sup>2</sup> by optimization of halo implantation and gate oxidation process. Pulse nitridation is applied to suppress Vth variations. Obtained characteristics of MOSFET places top class among devices reported. High density SRAM for CMOS5L with the cell size of 0.495μm<sup>2</sup> is developed. We demonstrate highly stable operation by 7Mb CMOS5L SRAM array. This SRAM has low power property less than 100μW.
    VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
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    ABSTRACT: It has been reported that the dynamic recovery of drain current (I<sub>d</sub>) takes place soon after the stress applied on the gate is removed during a MOSFET negative bias temperature instability (NBTI) experiment. This phenomenon makes it very difficult to estimate the NBTI degradation of I<sub>d</sub> (ΔI<sub>d</sub>) correctly. The paper presents a new characterization method in which the effect of the dynamic recovery is quantitatively taken into account to estimate ΔI<sub>d</sub> precisely.
    Microelectronic Test Structures, 2005. ICMTS 2005. Proceedings of the 2005 International Conference on; 05/2005
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    ABSTRACT: We show new constraint of Vth scaling for logic blocks from inverter operation viewpoint. In lower Vth region, delay time in inverter chain saturates because of the loss in overdrive for the input of MOSFETs. This loss dominates the inverter speed in scaled V dd region and we propose a new relaxed scaling scenario. This accounts for the speed loss using a simplified model which adequately manifests the new phenomenon
    01/2005;
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    ABSTRACT: We show new guideline of Vdd and Vth scaling for logic blocks and high density SRAM cell from low power dissipation viewpoint. New degradation mode for inverter delay becomes major obstacle for Vdd scaling in the future. Low Vdd and low Vth should be applied only for circuits with high switching activity. In other portions, Vdd should be kept around 1-1.2V. High density SRAM with beta ratio of 1(0.56 μm<sup>2</sup>) operates at 0.7V by choosing optimum Vth.
    VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on; 07/2004
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    ABSTRACT: 65 nm node SoC technology has been achieved to show good yield of 8 Mbit DRAM ADM using tapered BF<sub>2</sub> implantation without an additional mask step, the cell size of which is 0.11 μm<sup>2</sup>, with 3 layers of hybrid low-k material, SiLK/BD/BLOk, and Cu integration.
    Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International; 01/2004
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    ABSTRACT: We show very high density embedded 6T-SRAM cell of 0.56 μm<sup>2</sup>. This is the smallest value reported so far. Developed embedded SRAM cell achieves adequate SNM of 90 mV at 0.6 V on high performance 65 nm SoC platform (CMOS5).
    VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on; 07/2003
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    ABSTRACT: In this paper, we demonstrate high performance CMOS devices developed for the 65 nm technology node. The gate length is shrunk down to 30 nm. The gate oxide is nitrided oxide of 1 nm EOT with an abrupt nitrogen profile. In order to satisfy both the high activation of the gate polysilicon and suppression of the short channel effect, we applied high dose PMOS doping and low temperature spike anneal to the source and drain. Junction leakage is suppressed by applying nickel silicide in such shallow deep junctions. At a supply voltage of 0.85 V, high drive currents (700 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for nMOSFET and 300 /spl mu/A//spl mu/m at Ioff=100 nA//spl mu/m for pMOSFET) and low CV/I values (0.71 ps at Ioff=100 nA//spl mu/m for nMOSFET and 1.41 ps at Ioff=100 nA//spl mu/m for pMOSFET) are achieved. They are the best among published data.
    Electron Devices Meeting, 2002. IEDM '02. International; 01/2003
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    ABSTRACT: In this paper, we present a 65 nm CMOS technology for high performance SoC (system-on-chip), especially for broadband core chip applications. Logic gate length is scaled down to 30 nm, and embedded SRAM cell size is shrunk to 0.6 /spl mu/m/sup 2/. Embedded DRAM cell size is 0.11 /spl mu/m/sup 2/. MOSFET's in this technology have high nitrogen concentration plasma nitrided oxide gate dielectrics to suppress gate leakage current. Furthermore poly-SiGe gate electrode and Ni Salicide were adopted to control high gate electrode activation and USJ (ultra shallow junctions) under low thermal budget. Hi-NA193-nm lithography with alternating phase shift mask and the slimming process combined with non-slimming trim mask process were employed to achieve a small SRAM cell. Cu interconnects; using low-k dielectrics has an 180 nm pitch.
    Electron Devices Meeting, 2002. IEDM '02. International; 02/2002
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    ABSTRACT: In this paper, we focus on hydrogen related processes and its impact on system LSI. Hydrogen affects not only DRAM performance but also reliability characteristics for MOSFET such as NBTI (negative bias temperature instability), HCI (hot carrier injection), and TDDB. We demonstrate that NBTI and HCI are degraded by excess hydrogen while improving retention characteristics of eDRAM. It is shown for the first time that anomalous degradation in TDDB for downsized MOSFET is caused by the compressive stress by STI and shows strong correlation to hydrogen processes. The optimization of hydrogen processes is indispensable for highly reliable system LSI in future generations.
    VLSI Technology, 2002. Digest of Technical Papers. 2002 Symposium on; 02/2002