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ABSTRACT: Type-II charge-pump (CP) phase-locked loop (PLLs) are used extensively in electronic systems for frequency synthesis. Recently, a passive sampled loop filter (SLF) has been shown to offer major benefits over the conventional continuous-time loop filter traditionally used in such PLLs. These benefits include greatly enhanced reference spur suppression, elimination of CP pulse-position modulation nonlinearity, and, in the case of phase noise cancelling fractional-N PLLs, improved phase noise cancellation. The main disadvantage of the SLF to date has been the lack of a linear time-invariant (LTI) model with which to perform the system-level design of SLF-based PLLs. Without such a model, designers are forced to rely on trial and error iteration supported by lengthy transient simulations. This paper presents an accurate LTI model of SLF-based type-II PLLs that eliminates this disadvantage.
Circuits and Systems I: Regular Papers, IEEE Transactions on 03/2011; · 1.97 Impact Factor
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ABSTRACT: This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together facilitate low-voltage operation and enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs. The pipelined ADC achieves a peak SNR of 70 dB and a -1 dBFS SFDR of 85 dB at a sample-rate of 100 MHz. It is implemented in a 90 nm CMOS process and consumes 130 mW from 1.2 V and 1.0 V analog and digital power supplies, respectively.
IEEE Journal of Solid-State Circuits 01/2010; · 3.23 Impact Factor
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ABSTRACT: Dynamic element matching (DEM) is widely used in multibit digital-analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performance-enabling technique in delta-sigma data converters which require low-resolution but high-linearity DACs. More recently, segmented DEM architectures have made high-resolution Nyquist-rate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff.
Circuits and Systems I: Regular Papers, IEEE Transactions on 01/2009; · 1.97 Impact Factor
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ABSTRACT: This paper demonstrates that spurious tones in the output of a fractional- N PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of - 70 dBc and a worst-case in-band fractional spur power of -64 dBc.
IEEE Journal of Solid-State Circuits 01/2009; · 3.23 Impact Factor
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ABSTRACT: A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm<sup>2</sup> and its core circuitry consumes 20.9 mA from a 1.8 V supply.
IEEE Journal of Solid-State Circuits 01/2008; · 3.23 Impact Factor
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ABSTRACT: A major problem in oversampling digital-to-analog converters and fractional-N frequency synthesizers, which are ubiquitous in modern communication systems, is that the noise they introduce contains spurious tones. The spurious tones are the result of digitally generated, quantized signals passing through nonlinear analog components. This paper presents a new method of digital requantization called successive requantization, special cases of which avoids the spurious tone generation problem. Sufficient conditions are derived that ensure certain statistical properties of the quantization noise, including the absence of spurious tones after nonlinear distortion. A practical example is presented and shown to satisfy these conditions.
IEEE Transactions on Signal Processing 12/2007; · 2.63 Impact Factor
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ABSTRACT: A segmented DEM technique that allows an efficient tradeoff between encoder complexity and the number of unit current-steering cells enables a 150 MS/s DAC with greater than 83 dB of SFDR across the Nyquist band. The 0.18 mum CMOS IC has an active area of 3 mm<sup>2</sup> and dissipates 127 mW.
VLSI Circuits, 2007 IEEE Symposium on; 07/2007
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ABSTRACT: Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta-sigma (DeltaSigma) modulator in a multistage digital DeltaSigma modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither's contribution to the power spectral density of the multistage digital DeltaSigma modulator's output. A large class of popular multistage digital DeltaSigma modulators that satisfy the conditions are identified and tabulated for easy reference
Circuits and Systems I: Regular Papers, IEEE Transactions on 05/2007; · 1.97 Impact Factor
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ABSTRACT: An analysis of the quantization noise introduced by a widely-used class of single-quantizer digital delta-sigma (DeltaSigma) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the quantization noise such as uniformity and independence from the input and delayed versions of itself. The conditions are also shown to be sufficient for a single realization of the quantization noise sequence to possess these properties in a time-averaged sense. Several of the most commonly-used digital DeltaSigma modulators are shown to satisfy the conditions
Circuits and Systems I: Regular Papers, IEEE Transactions on 04/2007; · 1.97 Impact Factor
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ABSTRACT: A 2.4GHz ISM-band PLL with a 730kHz bandwidth, a 12MHz reference, an on-chip loop filter, and worst-case phase noise of -101 dBc/Hz and -124dBc/Hz at 100kHz and 3MHz offsets, respectively, is enabled by an adaptive phase-noise cancellation technique with 35mus settling time. The 0.18mum CMOS IC measures 2.2times2.2mm<sup>2</sup>, and its core circuitry draws 20.9mA from a 1.8V supply.
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International; 03/2007
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ABSTRACT: Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs
Circuits and Systems I: Regular Papers, IEEE Transactions on 10/2006; · 1.97 Impact Factor
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ABSTRACT: A novel digital frequency synthesis (DDS) architecture with a 1-bit output is proposed, simulated, and demonstrated. A new noise shaping quantization algorithm is also evaluated and used within the proposed DDS system. Large tuning ranges and rapid (open loop) response characteristics are achieved with only a static reference frequency input, without the use of analog components, allowing easy integration in digital CMOS processes. Across a tuning range of 10% f<sub>ref</sub>, a noise floor of -80 dBc/Hz and spurious tones lower than -50 dBc are possible with this system
Microwave Symposium Digest, 2006. IEEE MTT-S International; 07/2006
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ABSTRACT: A 14b 100MS/s Nyquist-rate DAC using a segmented dynamic-element-matching technique involving all the DAC elements is demonstrated. The DAC is implemented in a 0.18mum CMOS process and worst-case SFDRs across Nyquist bands are 74.4dB and 78.9dB for sample-rates of 100MS/s and 70Ms/s, respectively
Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International; 03/2006
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IEEE Journal of Solid-State Circuits 03/2005; · 3.23 Impact Factor
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Wireless and Microwave Technology, 2005. WAMICON 2005. The 2005 IEEE Annual Conference; 02/2005
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ABSTRACT: A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signal-to-noise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a low-latency, segmented, dynamic element-matching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the first-stage residue amplifier to settle. The IC is realized in a 0.18-μm mixed-signal CMOS process and has a die size of 4mm×5 mm.
IEEE Journal of Solid-State Circuits 01/2005; · 3.23 Impact Factor
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ABSTRACT: Nonlinearity characterization is critical to amplifier linearization. It is shown that correlation techniques can be used to provide an estimate of amplifier nonlinearity. The output envelope is cross-correlated with a test sequence generated by forming the product of multiple uncorrelated input sequences, to yield estimates of the low order nonlinearity coefficients. The proposed method can be employed in the background during amplifier operation to estimate amplifier nonlinearity with IS-95 forward-link CDMA signals.
Radio and Wireless Conference, 2004 IEEE; 10/2004
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ABSTRACT: This paper presents two techniques for reducing phase noise in recirculating delay-locked loops (DLLs) and extends recently developed theoretical results to optimize the performance of a recirculating DLL prototype CMOS IC incorporating the techniques. One of the techniques reduces 1/f noise in both the voltage-controlled oscillator (VCO) and bias circuitry through hard periodic switching of key transistors. The other technique maximizes the phase noise suppression achieved by periodically switching in a clean reference pulse to reset the VCO phase noise memory. Theoretical results are used to optimize the loop filter and establish several general design guidelines for recirculating DLLs. Measured performance data from the fabricated IC with and without the techniques enabled closely support the theoretical predictions.
IEEE Journal of Solid-State Circuits 09/2004; · 3.23 Impact Factor
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ABSTRACT: Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise , limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal's frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits.
IEEE Transactions on Information Theory 05/2004; · 3.01 Impact Factor
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ABSTRACT: A 1.8 V 15 b 40 MS/s CMOS pipelined ADC with 90 dB SFDR and 72 dB peak SNR over the full Nyquist band is described. ADC performance is enhanced by digital background calibration of DAC noise and interstage gain error. The IC is realized in a 0.18 μm CMOS process, consumes 400 mW, and has a die size of 4 mm×5 mm.
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International; 03/2004
