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Guoliang Li, Ying Luo,
Xuezhe Zheng,
Gianlorenzo Masini,
Attila Mekis,
Subal Sahni,
Hiren Thacker,
Jin Yao,
Ivan Shubin,
Kannan Raj,
John E Cunningham,
Ashok V Krishnamoorthy
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ABSTRACT: We report design improvements for evanescently coupled Germanium photodetectors grown at low temperature. The resulting photodetectors with 10 μm Ge length manufactured in a commercial CMOS process achieve >0.8 A/W responsivity over the entire C-band, with a device capacitance of <7 fF based on measured data.
Optics Express 11/2012; 20(24):26345-50. · 3.59 Impact Factor
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Dazeng Feng,
Shirong Liao,
Hong Liang,
Joan Fong,
Bhavin Bijlani,
Roshanak Shafiiha,
B Jonathan Luff, Ying Luo,
Jack Cunningham,
Ashok V Krishnamoorthy,
Mehdi Asghari
[show abstract]
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ABSTRACT: We demonstrate a high speed GeSi electro-absorption (EA) modulator monolithically integrated on 3 µm silicon-on-insulator (SOI) waveguide. The demonstrated device has a compact active region of 1.0 × 55 μm<sup>2</sup>, an insertion loss of 5 dB and an extinction ratio of 6 dB at wavelength of 1550 nm. The modulator has a broad operating wavelength range of 35 nm and a 3 dB bandwidth of 40.7 GHz at 2.8 V reverse bias. This compact and energy efficient modulator is a key building block for optical interconnection applications.
Optics Express 09/2012; 20(20):22224-32. · 3.59 Impact Factor
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Guoliang Li,
Jin Yao,
Hiren Thacker,
Attila Mekis,
Xuezhe Zheng,
Ivan Shubin, Ying Luo,
Jin-Hyoung Lee,
Kannan Raj,
John E Cunningham,
Ashok V Krishnamoorthy
[show abstract]
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ABSTRACT: We report optical waveguides up to one meter long with 0.026 dB/cm loss fabricated in a 300nm thick SOI CMOS process. Combined with tight bends and compact interlayer grating couplers, we demonstrate a complete toolbox for ultralow-loss, high-density waveguide routing for macrochip interconnects.
Optics Express 05/2012; 20(11):12035-9. · 3.59 Impact Factor
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[show abstract]
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ABSTRACT: We show enhanced optical bistability induced by free carrier absorption from junction doping in substrate-removed silicon ring modulators. Such linear thermal effects dominate the loss in high-speed depletion silicon ring modulators. Optical bistability was observed with about 100 μW of input optical power. We further show that such thermal interactions causes data-dependent ring resonance shifts, and consequently severely degrade the data modulation quality at low speeds. The frequency response of this effect was measured to be about 100~200 kHz.
Optics Express 05/2012; 20(10):11478-86. · 3.59 Impact Factor
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[show abstract]
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ABSTRACT: We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint.
Optics Express 10/2011; 19(21):20435-43. · 3.59 Impact Factor
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H.D. Thacker,
I. Shubin, Ying Luo,
J. Costa,
J. Lexau,
Xuezhe Zheng,
Guoliang Li,
Jin Yao,
Jieda Li,
D. Patil,
F. Liu,
R. Ho,
Dazeng Feng,
M. Asghari,
T. Pinguet,
K. Raj,
J.G. Mitchell,
A.V. Krishnamoorthy,
J.E. Cunningham
[show abstract]
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ABSTRACT: Oracle's scalable hybrid integration technology platform enables continuing improvements in performance and energy efficiency of photonic bridge chips by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultralow power high-performance photonic interconnects for future computing systems. Herein, we report on our second generation of photonic bridge chips comprising electronic drivers and receivers built in 40 nm bulk CMOS technology attached to nanophotonic devices, fabricated using SOI-photonic and 130 nm SOI-CMOS photonic technologies. Hybrid integration by flip-chip bonding is enabled by microsolder bump interconnects scaled down from our previous generation effort and fabricated on singulated dies by a novel batch processing technique based on component embedding. Generation-on-generation, the hybrid integrated Tx and Rx bridge chips achieved 2.3× and 1.7× improvement in energy efficiency, respectively, while operating at 2× the datarate (10 Gbps).
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st; 07/2011
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J.E. Cunningham,
A.V. Krishnamoorthy,
Ron Ho,
I. Shubin,
H. Thacker,
J. Lexau,
D.C. Lee,
Dazeng Feng,
E. Chow, Ying Luo,
Xuezhe Zheng,
Guoliang Li,
Jin Yao,
T. Pinguet,
K. Raj,
M. Asghari,
J.G. Mitchell
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ABSTRACT: The technologies associated with integration and packaging have a significant impact on the overall system. In this paper, we review a silicon photonic “macrochip” system and its associated packaging that will allow dense wavelength-division multiplexed optical links to be intimately integrated and co-manufactured with the switching electronics. For this to happen, we anticipate a number of integration and packaging advances.
IEEE Journal of Selected Topics in Quantum Electronics 07/2011; · 3.78 Impact Factor
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Shirong Liao,
Ning-Ning Feng,
Dazeng Feng,
Po Dong,
Roshanak Shafiiha,
Cheng-Chih Kung,
Hong Liang,
Wei Qian,
Yong Liu,
Joan Fong,
John E Cunningham, Ying Luo,
Mehdi Asghari
[show abstract]
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ABSTRACT: We present two effective approaches to improve the responsivity of high speed waveguide-based Ge photodetectors integrated on a 0.25 μm silicon-on-insulator (SOI) platform. The main cause of poor responsivity is identified as metal absorption from the top contact to Ge. By optimizing Ge thickness and offsetting the contact window, we have demonstrated that the responsivity can be improved from 0.6A/W to 0.95 A/W at 1550 nm with 36 GHz 3 dB bandwidth. We also demonstrate that a wider device with double offset contacts can achieve 1.05 A/W responsivity at 1550 nm and 20 GHz 3 dB bandwidth.
Optics Express 05/2011; 19(11):10967-72. · 3.59 Impact Factor
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Ning-Ning Feng,
Shirong Liao,
Dazeng Feng,
Xin Wang,
Po Dong,
Hong Liang,
Cheng-Chih Kung,
Wei Qian,
Yong Liu,
Joan Fong,
Roshanak Shafiiha, Ying Luo,
Jack Cunningham,
Ashok V Krishnamoorthy,
Mehdi Asghari
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ABSTRACT: We present the design and fabrication of a waveguide-based Ge electro-absorption (EA) modulator integrated with a 3 µm silicon-on-isolator (SOI) waveguide. The proposed Ge EA modulator employs a butt-coupled horizontally-oriented p-i-n structure. The optical design achieves a low-loss transition from Ge to Si waveguides. The interaction between the optical mode of the waveguide and the bias induced electric field in the p-i-n structure was maximized to achieve high modulation efficiency. By balancing the trade-offs between the extinction ratio and the insertion loss of the device, an optimal working regime was identified. The measurement results from a fabricated device were used to verify the design. Under a -4Vpp reverse bias, the device demonstrates a total insertion loss (including the transition loss) of 2.7-5.2 dB and an extinction ratio of 4.9-8.2 dB over the wavelength range of 1610-1640 nm. Subtracting the contribution of the transition loss, the Δα/α value for the fabricated device was estimated to be between 2.2 and 3.2 with an electric field around 55 kV/cm.
Optics Express 04/2011; 19(9):8715-20. · 3.59 Impact Factor
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Ashok V Krishnamoorthy,
Xuezhe Zheng,
Guoliang Li,
Jin Yao,
Thierry Pinguet,
Attila Mekis,
Hiren Thacker,
Ivan Shubin, Ying Luo,
Kannan Raj,
John E Cunningham
[show abstract]
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ABSTRACT: We present manufacturing tolerances of cascaded silicon microring resonators fabricated in a commercial 130-nm complementary-oxide semiconductor (CMOS) foundry using 193-nm lithography and provide statistics gathered from over 500 four-channel microring arrays over multiple wafers and fabrication lots. We quantify intrawafer and interwafer variation of the position and relative spacing of resonance wavelengths for the microring arrays and confirm prior predictions that the absolute resonance positions of such devices cannot be controlled across wafers or even across reticles within a wafer. However, we show that the free spectral range (FSR) of the microrings can be controlled to within 0.66 nm (83 GHz) across wafers and lots, as can the wavelength spacing between closely spaced microrings. To exploit these findings for low-power optical interconnects, we suggest and demonstrate a synthetic resonant comb with FSR % N Ã , wherein resonance wavelengths are spaced equally across the FSR in order to minimize postfabrication tuning. The experimental CMOS 1 Â 8 microring array requires an average tuning of less than 1.2 nm/ channel to align to a 200-GHz wavelength division multiplexing (WDM) grid. Monte Carlo simulations on 100 000 sample runs show that an average tuning of 1.72 nm/channel is sufficient for 99% coverage for this component. This indicates that it is possible, with high statistical confidence, to use high-volume CMOS manufacturing to reduce the tuning range and tuning energy requirements of silicon microrings and, hence, enhance their ability to be used in high-density, energy-efficient computing system applications.
04/2011;
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Ning-Ning Feng,
Dazeng Feng,
Shirong Liao,
Xin Wang,
Po Dong,
Hong Liang,
Cheng-Chih Kung,
Wei Qian,
Joan Fong,
Roshanak Shafiiha, Ying Luo,
Jack Cunningham,
Ashok V Krishnamoorthy,
Mehdi Asghari
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate a compact waveguide-based high-speed Ge electro-absorption (EA) modulator integrated with a single mode 3 µm silicon-on-isolator (SOI) waveguide. The Ge EA modulator is based on a horizontally-oriented p-i-n structure butt-coupled with a deep-etched silicon waveguide, which transitions adiabatically to a shallow-etched single mode large core SOI waveguide. The demonstrated device has a compact active region of 1.0 × 45 µm(2), a total insertion loss of 2.5-5 dB and an extinction ratio of 4-7.5 dB over a wavelength range of 1610-1640 nm with -4V(pp) bias. The estimated Δα/α value is in the range of 2-3.3. The 3 dB bandwidth measurements show that the device is capable of operating at more than 30 GHz. Clear eye-diagram openings at 12.5 Gbps demonstrates large signal modulation at high transmission rate.
Optics Express 04/2011; 19(8):7062-7. · 3.59 Impact Factor
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Xuezhe Zheng,
Dinesh Patil,
Jon Lexau,
Frankie Liu,
Guoliang Li,
Hiren Thacker, Ying Luo,
Ivan Shubin,
Jieda Li,
Jin Yao, [......],
Attila Mekis,
Philip Amberg,
Michael Dayringer,
Jon Gainsley,
Hesam Fathi Moghadam,
Elad Alon,
Kannan Raj,
Ron Ho,
John E Cunningham,
Ashok V Krishnamoorthy
[show abstract]
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ABSTRACT: Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved electro-optic efficiency to allow stepper optical photo lithography for reduced fabrication complexity. Integrated with a low power cascode 2 V CMOS driver, the hybrid silicon photonic transmitter achieved better than 7 dB extinction ratio for 10 Gbps operation with a record low power consumption of 1.35 mW. A received power penalty of about 1 dB was measured for a BER of 10(-12) compared to an off-the-shelf lightwave LiNOb3 transmitter, which comes mostly from the non-perfect extinction ratio. Similarly, a Ge waveguide detector fabricated using 130 nm SOI CMOS process was integrated with low power VLSI circuits using hybrid bonding. The all CMOS hybrid silicon photonic receiver achieved sensitivity of -17 dBm for a BER of 10(-12) at 10 Gbps, consuming an ultra-low power of 3.95 mW (or 395 fJ/bit in energy efficiency). The scalable hybrid integration enables continued photonic device improvements by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultra-low power high performance photonic interconnects for future computing systems.
Optics Express 03/2011; 19(6):5172-86. · 3.59 Impact Factor
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Xuezhe Zheng,
J.E. Cunningham,
R. Ho,
J. Lexau,
Guoliang Li, Ying Luo,
H. Thacker,
Jin Yao,
F. Liu,
D. Patil,
P. Amberg,
N. Pinckney,
Po Dong,
Dazeng Feng,
M. Asghari,
A. Mekis,
T. Pinguet,
K. Raj,
A.V. Krishnamoorthy
[show abstract]
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ABSTRACT: We present ultra low power silicon photonic transceivers, including a 320 fJ/bit reverse biased ring modulator integrated with CMOS driver, and a 690 fJ/bit record-low power receiver with sensitivity of -18.9 dBm at 5 Gbps for bit-error-rate of 10<sup>-12</sup>.
Photonics Society Summer Topical Meeting Series, 2010 IEEE; 08/2010
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Xuezhe Zheng,
John E. Cunningham,
Guoliang Li, Ying Luo,
Hiren Thacker,
Jin Yao,
Ron Ho,
Jon Lexau,
Frankie Liu,
Dinesh Patil,
Philip Amberg,
Nathaniel Pinckney,
Po Dong,
Dazeng Feng,
Mehdi Asghari,
Attila Mekis,
Thierry Pinguet,
Kannan Raj,
Ashok V. Krishnamoorthy
[show abstract]
[hide abstract]
ABSTRACT: Scaling of high performance, many-core, computing systems calls for disruptive solutions to provide ultra energy efficient and high bandwidth density interconnects at very low cost. Silicon photonics is viewed as a promising solution. For silicon photonics to prevail and penetrate deeper into the computing system interconnection hierarchy, it requires innovative optical devices, novel circuits, and advanced integration. We review our recent progress in key building blocks toward sub pJ/bit optical link for inter/intra-chip applications, ultra-low power silicon photonic transceivers. In particular, compact reverse biased silicon ring modulator was developed with high modulation bandwidth sufficient for 15Gbps modulation, very small junction capacitance of ~50fF, low voltage swing of 2V, high extinction ratio (>7dB) and low optical loss (~2dB at on-state). Integrated with low power CMOS driver circuits using low parasitic microsolder bump technique, we achieved record low power consumption of 320fJ/bit at 5Gbps data rate. Stable operation with biterror- rate better than 10-13 was accomplished with simple thermal management. We further review the first hybrid integrated silicon photonic receiver based on Ge waveguide photo detector using the same integration technique, with which high energy efficiency of 690fJ/bit, and sensitivity of ~18.9dBm at 5Gbps data rate for bit-error-rate of 10-12 were achieved.© (2010) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
08/2010;
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John E Cunningham,
Ivan Shubin,
Xuezhe Zheng,
Thierry Pinguet,
Attila Mekis, Ying Luo,
Hiren Thacker,
Guoliang Li,
Jin Yao,
Kannan Raj,
Ashok V Krishnamoorthy
[show abstract]
[hide abstract]
ABSTRACT: We demonstrate spectral tunability for microphotonic add-drop filters manufactured as ring resonators in a commercial 130 nm SOI CMOS technology. The filters are provisioned with integrated heaters built in CMOS for thermal tuning. Their thermal impedance has been dramatically increased by the selective removal of the SOI handler substrate under the device footprint using a bulk silicon micromachining process. An overall ~20x increase in the tuning efficiency has been demonstrated with a 100 µm radius ring as compared to a pre-micromachined device. A total of 3.9 mW of applied tuning power shifts the filter resonant peak across one free spectral node of the device. The Q-factor of the resonator remains unchanged after the co-integration process and hence this device geometry proves to be fully CMOS compatible. Additionally, after the cointegration process our result of 2π shift with 3.9 mW power is among the best tuning performances for this class of devices. Finally, we examine scaling the tuning efficiency versus device footprint to develop a different performance criterion for an easier comparison to evaluate thermal tuning. Our criterion is defined as the unit of power to shift the device resonance by a full 2π phase shift.
Optics Express 08/2010; 18(18):19055-63. · 3.59 Impact Factor
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Hiren D. Thacker, Ying Luo,
Jing Shi,
Ivan Shubin,
Jon Lexau,
Xuezhe Zheng,
Guoliang Li,
Jin Yao,
Joannes Costa,
Thierry Pinguet,
Attila Mekis,
Po Dong,
Shirong Liao,
Dazeng Feng,
Mehdi Asghari,
Ron Ho,
Kannan Raj,
James G. Mitchell,
Ashok V. Krishnamoorthy,
John E. Cunningham
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ABSTRACT: Silicon photonics holds tremendous promise as an energy and bandwidth efficient interconnect technology for chip-to-chip and within-chip communications in high-performance computing systems. In this paper, we present a low-parasitic microsolder-based flip-chip integration method used to integrate silicon photonic modulators and photodetectors with high-speed VLSI circuits using chips fabricated on vastly different technology platforms. Both the hybrid-integrated silicon photonic transmit (Tx) and receive (Rx) components were tested to demonstrate record sub-picojoule-per-bit performance at 5 Gbps.
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th; 07/2010
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Xuezhe Zheng,
Ivan Shubin,
Guoliang Li,
Thierry Pinguet,
Attila Mekis,
Jin Yao,
Hiren Thacker, Ying Luo,
Joey Costa,
Kannan Raj,
John E Cunningham,
Ashok V Krishnamoorthy
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ABSTRACT: We report the first compact silicon CMOS 1x4 tunable multiplexer/ demultiplexer using cascaded silicon photonic ring-resonator based add/drop filters with a radius of 12 microm, and integrated doped-resistor thermal tuners. We measured an insertion loss of less than 1 dB, a channel isolation of better than 16 dB for a channel spacing of 200 GHz, and a uniform 3 dB pass band larger than 0.4 nm across all four channels. We demonstrated accurate channel alignment to WDM ITU grid wavelengths using integrated silicon heaters with a tuning efficiency of 90 pm/mW. Using this device in a 10 Gbps data link, we observed a low power penalty of 0.6 dB.
Optics Express 03/2010; 18(5):5151-60. · 3.59 Impact Factor
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Xuezhe Zheng,
Jon Lexau, Ying Luo,
Hiren Thacker,
Thierry Pinguet,
Attila Mekis,
Guoliang Li,
Jing Shi,
Philip Amberg,
Nathaniel Pinckney,
Kannan Raj,
Ron Ho,
John E Cunningham,
Ashok V Krishnamoorthy
[show abstract]
[hide abstract]
ABSTRACT: We report the first sub-picojoule per bit (400fJ/bit) operation of a silicon modulator intimately integrated with a driver circuit and embedded in a clocked digital transmitter. We show a wall-plug power efficiency below 400microW/Gbps for a 130nm SOI CMOS carrier-depletion ring modulator flip-chip integrated to a 90nm bulk Si CMOS driver circuit. We also demonstrate stable error-free transmission of over 1.5 petabits of data at 5Gbps over 3.5 days using the integrated modulator without closed-loop ring resonance tuning. Small signal measurements of the CMOS ring modulator, sans circuit, showed a 3dB bandwidth in excess of 15GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit is possible while retaining compatibility with CMOS drive voltages.
Optics Express 02/2010; 18(3):3059-70. · 3.59 Impact Factor
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Xuezhe Zheng,
Frankie Liu,
Dinesh Patil,
Hiren Thacker, Ying Luo,
Thierry Pinguet,
Attila Mekis,
Jin Yao,
Guoliang Li,
Jing Shi,
Kannan Raj,
Jon Lexau,
Elad Alon,
Ron Ho,
John E Cunningham,
Ashok V Krishnamoorthy
[show abstract]
[hide abstract]
ABSTRACT: We report ultra-low-power (690fJ/bit) operation of an optical receiver consisting of a germanium-silicon waveguide detector intimately integrated with a receiver circuit and embedded in a clocked digital receiver. We show a wall-plug power efficiency of 690microW/Gbps for the photonic receiver made of a 130nm SOI CMOS Ge waveguide detector integrated to a 90nm Si CMOS receiver circuit. The hybrid CMOS photonic receiver achieved a sensitivity of -18.9dBm at 5Gbps for BER of 10(-12). Enabled by a unique low-overhead bias refresh scheme, the receiver operates without the need for DC balanced transmission. Small signal measurements of the CMOS Ge waveguide detector showed a 3dB bandwidth of 10GHz at 1V of reverse bias, indicating that further increases in transmission rate and reductions of energy-per-bit will be possible.
Optics Express 01/2010; 18(1):204-11. · 3.59 Impact Factor
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Guoliang Li,
Xuezhe Zheng,
Jon Lexau, Ying Luo,
Hiren Thacker,
Thierry Pinguet,
Po Dong,
Dazeng Feng,
Shirong Liao,
Roshanak Shafiiha,
Mehdi Asghari,
Jin Yao,
Jing Shi,
Ivan N Shubin,
Dinesh Patil,
Frankie Liu,
Kannan Raj,
Ron Ho,
John E Cunningham,
Ashok V Krishnamoorthy
[show abstract]
[hide abstract]
ABSTRACT: The Ultra-performance Nanophotonic Intrachip Communication (UNIC) project aims to achieve unprecedented high-density, low-power, large-bandwidth, and low-latency optical interconnect for highly compact supercomputer systems. This project, which has started in 2008, sets extremely aggressive goals on power consumptions and footprints for optical devices and the integrated VLSI circuits. In this paper we will discuss our challenges and present some of our first-year achievements, including a 320 fJ/bit hybrid-bonded optical transmitter and a 690 fJ/bit hybrid-bonded optical receiver. The optical transmitter was made of a Si microring modulator flip-chip bonded to a 90nm CMOS driver with digital clocking. With only 1.6mW power consumption measured from the power supply voltages and currents, the transmitter exhibits a wide open eye with extinction ratio >7dB at 5Gb/s. The receiver was made of a Ge waveguide detector flip-chip bonded to a 90nm CMOS digitally clocked receiver circuit. With 3.45mW power consumption, the integrated receiver demonstrated -18.9dBm sensitivity at 5Gb/s for a BER of 10 -12 . In addition, we will discuss our Mux/Demux strategy and present our devices with small footprints and low tuning energy.
