[show abstract][hide abstract] ABSTRACT: A novel field-effect transistor with Si nanowire (NW) channels is developed and characterized. To enhance the film crystallinity, metal-induced lateral crystallization (MILC) and/or rapid thermal annealing (RTA) techniques are adopted in the fabrication. In the implementation of MILC process, it is shown that the arrangement of seeding window plays an important role in affecting the resulting film structure. In this regard, asymmetric window arrangement, i.e., with the window locating on only one of the two channel sides is preferred. When MILC and RTA techniques are combined, it is found that single-crystal-like NWs are achieved, leading to significant performance improvement as compared with the control with channels made up of fine-grain structures by the conventional solid-phase crystallized (SPC) approach. Field-effect mobility up to 550 cm<sup>2</sup>/V-s is recorded in this study
IEEE Transactions on Nanotechnology 04/2007; · 1.80 Impact Factor
[show abstract][hide abstract] ABSTRACT: Characteristics of n-channel metal-oxide-semiconductor field-effect transistors with SiN capping were investigated in this work. Although the SiN capping could dramatically enhance the carrier mobility and thus the device drive current, the resistance to hot-carrier degradation is compromised as well, owing to the large amount of hydrogen contained in the SiN layer which may diffuse into the channel region during the process. To eliminate this shortcoming, the insertion of an ultrathin (10 nm) polycrystalline-silicon buffer layer between the gate and the SiN capping was proposed and demonstrated to restore the hot-carrier reliability of the devices without compromising the current enhancement due to the SiN capping.
[show abstract][hide abstract] ABSTRACT: A test structure was proposed to investigate the spatial and temporal evolution of hot-carrier degradation in n-channel poly-Si thin-film transistors. Our experimental results clearly show that the initial damage during the early stage of hot-carrier stressing, which is still undetectable by conventional test structures, can be easily observed by the structure. In addition, the proposed test structure is also capable of resolving the evolution of the degradation along the channel, thus providing a powerful tool to study the location-dependent damage mechanisms.
Journal of Applied Physics 03/2007; 101(5):054518-054518-5. · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this study, we propose the electrical characteristics of nMOSFETs with local strained channel technique using SiN capping layer on Hi- or Cz-wafers. The nMOSFETs were fabricated on 6-in Hi- and Cz- wafers. Before passivation layer deposition, a 300 nm LPCVD SiN was deposited (denoted as SiN/Cz and SiN/Hi), while some wafers were deliberately skipped of the SiN deposition step to serve as the controls (denoted as Cz-control and Hi). For some SiN-capped nMOSFETs, a thin LPCVD-TEOS buffer layer (about 7 nm, denoted as SiN/Buffer/Cz and SiN/Buffer/Hi) was capped prior to the SiN deposition.
[show abstract][hide abstract] ABSTRACT: Both the presence of the SiN capping layer and the deposition process itself exert significant impacts on the device operation and the associated reliability characteristics. The accompanying bandgap narrowing, increased carrier mobility and hydrogen diffusion from the SiN capping process tend to worsen the hot-electron reliability. This work shows that, owing to the use of hydrogen-containing precursors, abundant hydrogen species is presumably incorporated in the oxide and may contribute to the hot-electron degradation, even if the SiN layer is removed later and the channel strain is relieved. Furthermore, by blocking the diffusion of hydrogen species, the devices with 20nm-thick TEOS buffer layer can effectively improve the hot-electron reliability without compromising the performance enhancement by the strain induced by the SiN capping. Optimization of both the thickness of buffer layer and SiN deposition process are thus essential to the implementation of the uniaxial strain in NMOS devices.
[show abstract][hide abstract] ABSTRACT: In this work, quantitative information for nonuniform hot-carrier degradation, especially under mild stressing condition, is investigated. A test structure capable of revealing hot-carrier degradations of polycrystalline silicon (poly-Si) thin-film transistors in specific portions of the channel is employed. Effective density-of-states (DOS) distributions at the damaged sites can be extracted using field-effect conductance method, thus providing an effective tool to evaluate the impact of hot-carrier degradations. By measuring along individual sections of the channel, it becomes possible to extract the DOS for the device as a whole. The combination of the proposed test structure and DOS extraction technique also provides a powerful tool for modeling and simulating current-voltage characteristics of thin-film transistors under hot-carrier stressing.
Journal of Applied Physics 01/2007; 102. · 2.21 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this study, we propose the electrical characteristics and reliability behaviors of nMOSFETs using SiN capping layer on Hi- or Cz-wafers on different channel directions.
[show abstract][hide abstract] ABSTRACT: The characteristics of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with a SiN capping layer were investigated in this study. Although the incorporation of the SiN capping layer markedly enhanced the carrier mobility and thus the drive current of the fabricated devices, the resistance to hot-carrier degradation was sacrificed, owing to the high content of hydrogen in the SiN layer that might diffuse to the channel region during the process. Even if the SiN layer was removed and the channel strain was released later, the hot-carrier degradation was severer than that in devices without SiN capping. Finally, the lateral distribution of generated interface states due to hot-carrier stress was also investigated in this study.
Japanese Journal of Applied Physics 01/2007; 46:2027-2031. · 1.07 Impact Factor
[show abstract][hide abstract] ABSTRACT: In this paper, devices with SiN film deposited by higher N2 flow rate and deposition temperature possess higher tensile stress and thus better device performance enhancement. In addition, the immunity to hot-carrier stress is also improved because of less H diffusion from the SiN film.
[show abstract][hide abstract] ABSTRACT: The local strained channel (LSC) technique is proposed to provide tensile strained channel in nMOSFETs. However, the device reliability associated with the strained device owing to the strain, and excess hydrogen and nitrogen incorporation from the deposited SiN layer is an imminent concern. In line with this, the incorporation of a thin LPCVD-TEOS buffer layer to improve the reliability performance has been proposed. In addition, hydrogen annealed wafers (Hi-wafer) have been reported having reduced oxygen defects in Czochralski (CZ) wafers, with improved microroughness and defect on the surface after high hydrogen annealing.
[show abstract][hide abstract] ABSTRACT: The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved on-current per unit width and better control over the short channel effects. The major conduction mechanism of the off-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure
IEEE Transactions on Electron Devices 11/2006; · 2.06 Impact Factor
[show abstract][hide abstract] ABSTRACT: The correlation between channel mobility gain (Deltamu), linear drain-current gain (DeltaI<sub>dlin</sub>), and saturation drain-current gain (DeltaIdsat) of nanoscale strained CMOSFETs are reported. From the plots of DeltaI<sub>dlin</sub> versus DeltaI<sub>dsat</sub> and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R<sub>SD,PSS</sub>) to channel resistance (R<sub>CH,PSS</sub>) of strained CMOSFETs can be extracted. By plotting Deltamu versus DeltaI<sub>dlin</sub>, the efficiency of Deltamu translated to DeltaI<sub>dlin</sub> is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the DeltaI<sub>dlin </sub>-to-Deltamu sensitivity is maintained until R<sub>SD,PSS</sub> becomes comparable to/or higher than R<sub>CH,PSS</sub>
IEEE Electron Device Letters 09/2006; · 2.79 Impact Factor
[show abstract][hide abstract] ABSTRACT: A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HC) degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified.
IEEE Electron Device Letters 08/2006; · 2.79 Impact Factor
[show abstract][hide abstract] ABSTRACT: We introduce, a complementary carbon nanotube (CNT)-gated CNT thin-film field effect transistor (FET). By using two perpendicularly crossed single-wall CNT (SWNT) bundles as the gate and the channel interchangeably, a sub-50 nm complementary CNT-FET is demonstrated. It is found that the new CNT-FET shows acceptable FET characteristics by interchanging the roles of the gate and the channel. The unique dual functionality of the device will open up a new possibility and flexibility in the design of future complementary CNT electronic circuits.
[show abstract][hide abstract] ABSTRACT: Channel backscattering ratios of PMOSFETs with various embedded SiGe source/drain structures are analyzed in terms of the scattering theory. We found that both the backscattering ratio and injection velocity are greatly influenced by the location and recess depth of SiGe source/drain. Although the strain-enhanced injection velocity is beneficial to the current gain, the accompanying backscattering ratio increase adversely impacts the overall performance, and therefore a trade-off exists between injection velocity and backscattering ratio during the optimization of such strain technique. The mechanism of increased backscattering ratio under uniaxial compressive strain is also investigated
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International; 01/2006
[show abstract][hide abstract] ABSTRACT: Depending on the chirality, single-walled carbon nanotubes (SWNTs) can be either metallic or semiconducting. Thus far, the production of SWNTs, irrespective of synthesis methods, still yields a mixture of both types, with the metallic type being prevalent. However, semiconducting-type SWNTs are needed for carbon nanotube field-effect transistors (CNT-FETs) as well as many sensors. This is because only the semiconducting-type SWNTs can be effectively modulated by the gate voltage. In contrast, the lack of field effect in metallic-type SWNTs adversely impacts their applications in high-performance electronic devices. In this study, we demonstrate for the first time a novel plasma treatment method that allows us to convert metallic-type carbon nanotubes to semiconducting-type CNT-FETs. On the basis of our experimental results, we believe that the ion bombardment during Ar plasma treatment attacks both metallic- and semiconducting-type nanotubes; however, the metallic-type carbon nanotubes are more vulnerable to the attack than those of the semiconducting type, and are subsequently transformed into the latter type.
Japanese Journal of Applied Physics 01/2006; 45:3680-3685. · 1.07 Impact Factor
[show abstract][hide abstract] ABSTRACT: This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.
Japanese Journal of Applied Physics 01/2006; 45:8611-8617. · 1.07 Impact Factor
[show abstract][hide abstract] ABSTRACT: The channel backscattering ratios as well as the ballistic efficiency of strained CMOSFETs were studied for both nondegenerate and degenerate-limited cases. We found that the simple nondegenerate assumption can predict strain-induced change of ballistic efficiency with fair accuracy. The mechanism of drain current dependence on strain-induced mobility change was also investigated based on channel backscattering theory