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Publications (2)0 Total impact

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    ABSTRACT: We propose an advanced DRAM cell structure with a capacitor formed after patterning the first-level metal. Since the second-level-metal which will be patterned after forming storage capacitors usually has a relaxed design rule, a sufficient cell capacitance can be obtained in this structure by simply increasing the stack height of the capacitor. A limited thermal cycle after the storage node formation makes it possible to use Ta<sub>2</sub>O<sub>5</sub> as a dielectric material without causing high temperature related leakage problems
    VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on; 07/1994
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    ABSTRACT: Micro villus patterning (MVP) technology which delivers the maximized cell capacitance is discussed. The key feature of the MVP technology is the formation of a hemispherical grain (HSG) archipelago and its transference to the underlayered oxide. The HSG archipelago pattern is produced on the oxide layer, and, by using that pattern as an etch mask, the oxide archipelago pattern is again transferred to the storage poly for the formation of villus bars by anisotropic dry etch. After the etching process, the oxide etch mask pattern is stripped away by using oxide wet etchant, so that additional Fin undercut structure is achieved underneath the main body. The main body of the storage electrode can be formed by single deposition and etch process, so that the storage electrode structure is strong enough to maintain its physical stability in spite of the complication of its shape. A 256-Mb DRAM-cell size of 0.6~0.8 μm<sup>2</sup> having more than 30 fF of cell capacitance with a stack structure, has been realized
    VLSI Technology, 1992. Digest of Technical Papers. 1992 Symposium on; 07/1992