Y Iwata

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Publications (2)3.23 Total impact

  • Article: Memory design using a one-transistor gain cell on SOI
    T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, K. Sunouchi
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    ABSTRACT: A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F<sup>2</sup> (F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F<sup>2</sup> cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C<sub>b</sub>/C<sub>s</sub>. free signal development drastically improve cell efficiency.
    IEEE Journal of Solid-State Circuits 12/2002; · 3.23 Impact Factor
  • Conference Proceeding: Memory design using one-transistor gain cell on SOI
    T Ohsawa, K Fujita, T Higashi, Y Iwata, T Kajiyama, Y. Asao, K. Sunouchi
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    ABSTRACT: A 512 kb DRAM has a 7F<sup>2</sup> one-transistor gain cell (F=0.18 μm) on SOI. The array driving method makes selective write possible. Basic operation is verified by device simulation and hardware measurement. Simulations show 40 ns access time. Non-destructive readout and Cb/Cs-free signal development improve cell efficiency
    Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International; 02/2002
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