Y I Kim

Publications (6)3.84 Total impact

• Conference Proceeding: High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond

  H.J. Oh, J.Y. Kim, J.H. Kim, S.G. Park, D.H. Kim, S.E. Kim, D.S. Woo, Y.S. Lee, G.W. Ha, J.M. Park, [......], M.H. Cho, Y.I. Kim, J. Choi, D.W. Shin, M.S. Shim, W.T. Choi, G.P. Lee, Y.J. Park, W.S. Lee, B.I. Ryu
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  ABSTRACT: For the first time, the DRAM device composed of 6F² open-bit-line memory cell with 80nm feature size is developed. Adopting 6F² scheme instead of customary 8F² scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F² accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F², TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V_th so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F² scheme. By adopting S-RCAT, V_th can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.
  Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European; 10/2005
• Conference Proceeding: S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

  J.V. Kim, H.J. Oh, D.S. Woo, Y.S. Lee, D.H. Kim, S.E. Kim, G.W. Ha, H.J. Kim, N.J. Kang, J.M. Park, [......], Y.I. Kim, C. Jin, D.W. Shin, M.S. Shim, C.S. Lee, W.S. Lee, J.C. Park, G.Y. Jin, Y.J. Park, Kinam Kim
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  ABSTRACT: For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.
  VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on; 07/2005
• Conference Proceeding: The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

  J.Y. Kim, D.S. Woo, H.J. Oh, H.J. Kim, S.E. Kim, B.J. Park, J.M. Kwon, M.S. Shim, G.W. Ha, J.W. Song, [......], Y.S. Lee, M.Y. Jung, Y.I. Kim, B.H. Lee, M.H. Cho, W.T. Choi, H.S. Kim, G.Y. Jin, Y.J. Park, Kinam Kim
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  ABSTRACT: The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.
  VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on; 05/2005
• Conference Proceeding: A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

  D.H. Kim, J.Y. Kim, M. Huh, Y.S. Hwang, J.M. Park, D.H. Han, D.I. Kim, M.H. Cho, B.H. Lee, H.K. Hwang, [......], S.S. Jeong, K.H. Yoon, T.H. Ahn, J.B. Lee, Y.W. Hyung, S.J. Park, W.T. Choi, G.Y. Jin, Y.G. Park, K. Kim
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  ABSTRACT: Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si₃N₄, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.
  Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International; 01/2005
• Conference Proceeding: A membrane capacitance measurement system for the study of exocytosis in secretory cells

  T.J. O'Shaughnessy, Y.I. Kim
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  ABSTRACT: A system for measuring exocytotic secretion in a single cell was developed utilizing an IBM compatible 386 PC. With sinusoidal excitation of the cells, a software based phase detection technique was implemented to monitor exocytosis-induced changes in membrane capacitance. The system is capable of monitoring exocytosis in response to either calcium or depolarizing voltage stimulation. The system has proven to be a useful tool in the study of changes in exocytosis produced by drugs and neurological disorders.
  Engineering in Medicine and Biology Society, 1992 14th Annual International Conference of the IEEE; 12/1992
• Article: Influence of helium I layer formation on the copper‐helium‐4 Kapitza resistance at helium II bath temperatures

  Y. I. Kim, Li‐He Lin, C. Chuang, T. H. K. Frederking
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  ABSTRACT: The transient Kapitza resistance between copper and helium II caused by a step input in power has been studied near 2 K. The resistance is affected by formation of a helium I layer whose thickness, of the order 10^-⁴–10^-⁵ cm, is evaluated as a function of the heat flux density.
  Applied Physics Letters 10/1983; · 3.84 Impact Factor