Z. Yang

IBM, Armonk, New York, United States

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Publications (5)0 Total impact

  • F. Guarin, Z. Yang, G. Freeman
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    ABSTRACT: We discuss the major reliability mechanisms and the implications arising from the structural changes required for the implementation of state of the art SiGe HBT's. The current gain shift under forward and reverse device operating conditions has been characterized for 120, 200 and 350 GHz transistors. The effects of electromigration and self-heating versus f<sub>T</sub> have also been studied. In general, it should be possible to continue scaling beyond today's 350 GHz devices, with straightforward extension of the mechanisms and concerns outlined in this paper
    Devices, Circuits and Systems, Proceedings of the 6th International Caribbean Conference on; 05/2006
  • Z. Yang, F. Guarin
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    ABSTRACT: We have studied the degradation in the off-state channel surface leakage current. This shift in the device leakage was found to be driven by a hot carrier mechanism in NMOS devices. The observed subthreshold current increase was studied and its origin was determined to be charging traps. The subsequent recovery of this electrical stress induced leakage current by the application of various gate bias conditions has also been documented and explained in this work. The implications of temperature, channel length and voltage conditions have been characterized
    01/2006;
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    ABSTRACT: A wafer-level technique to assess the forward current mode degradation of polysilicon emitter bipolar transistors has been developed. Using this technique, we show the successful implementation of a wafer level reliability (WLR) approach for the study of the degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f<sub>T</sub> and 100 GHz f<sub>max</sub>. Accelerated current stress as high as J<sub>c</sub>=34 mA/μm<sup>2</sup> was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. This technique was used to characterize the evolution of parametric shifts under current and temperature acceleration. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. A comparison of the WLR technique for heterojunction bipolar transistors (HBT) implemented in SiGe and III-V material systems is also provided. Through comparison with long term stress results performed on packaged transistors, we have verified their consistency with wafer level stressing, thus providing a viable WLR methodology for lifetime verification in a relatively short stress time and moderate temperature.
    Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on; 12/2004
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    ABSTRACT: In this paper, we focus on the reliability of SiGe HBTs related to scaling. HBT performance will continues to increase with no forceable significant reliability roadblocks. Designers will need to pay attention to the configuration and use conditions of the transistor.
    Compound Semiconductors, 2003. International Symposium on; 09/2003
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    ABSTRACT: A wafer-level reliability (WLR) technique is presented to assess the forward current mode degradation of polysilicon emitter bipolar transistors. Using this technique, we show results for the first time on degradation properties of high-speed self-aligned SiGe HBTs featuring 120 GHz f<sub>T</sub> and 100 GHz f<sub>max</sub>. Accelerated current stress up to as high as J<sub>C</sub>=34 mA/μm<sup>2</sup> was employed to assess the device degradation. It is shown that current accelerated stress may be used to effectively predict shifts in device characteristics. No catastrophic failures were observed, and thus this technique is used principally to demonstrate parametric shifts rather than end-of-life failures. Since the current stress also involves substantial self-heating of the device, we compare the degradation with temperature-only acceleration at both wafer and module level. It was found that the current acceleration is dominant over the temperature acceleration in the observable mechanisms. The mechanism for the parametric shifts is believed to be related to interfacial properties between the polysilicon and single-crystal portions of the device emitter. Through these studies, it is shown that the device is highly robust to parametric shifts for over 10<sup>6</sup> hours. The comparison with module level stress results verified their consistency with wafer level stressing, thus providing a viable WLR methodology for parameter shift projection in a relatively short stress time and moderate temperature.
    Reliability Physics Symposium Proceedings, 2002. 40th Annual; 02/2002