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ABSTRACT: We propose a cryptographic accelerator for IPsec by using the NEC electronics' dynamically reconfigurable processor (DRP). In our system, an embedded processor and DRP are integrated in a system-on-a-chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks on DRP. The evaluation results show that the throughput of each implemented cryptographic task outperformed a MIPS compatible embedded processor from 1.6 times to 7.8 times. In addition, it is shown that 80.7% of the run-time configuration overhead can be reduced by background configuration based on the double buffering method
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on; 01/2006
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ABSTRACT: Dynamically reconfigurable processors with multi-context facility have been used for various applications. The relationship between context size and performance of such processors is analyzed based on real designs. The parallelism diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the performance is degraded about 23% when the size of a context becomes 1/2. The performance per cost is improved 7-14 times than that of the case without time-multiplexed execution.
Field-Programmable Custom Computing Machines, 2005. FCCM 2005. 13th Annual IEEE Symposium on; 05/2005
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M. Suzuki, Y. Hasegawa,
Y. Yamada,
N. Kaneko,
K. Deguchi,
H. Amano,
K. Anjo,
M. Motomura,
K. Wakabayashi,
T. Toi,
T. Awashima
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ABSTRACT: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on; 01/2005
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N Suzuki,
S. Kurotaki,
M Suzuki,
N Kaneko,
Y Yamada,
K Deguchi, Y Hasegawa,
H Amano,
K. Anjo,
M Motomura,
K Wakabayashi,
T. Toi,
T. Awashima
[show abstract]
[hide abstract]
ABSTRACT: Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.
Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on; 05/2004
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ABSTRACT: Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a datapath called a context from the on-chip repository of sixteen circuit configurations at runtime. The time-multiplexed execution based on the multi-context functionality is expected to drastically improve area and power efficiency. To demonstrate the impact of the time-multiplexed execution, we have implemented several stream applications on DRP with various context sizes. Throughout the evaluation based on real application designs, we analyzed the impact of the time-multiplexed execution on performance and power dissipation quantitatively.
Parallel and Distributed Processing Symposium, International.
