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Publications (20)23.29 Total impact

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    ABSTRACT: Enhanced performance of RF power modules is required in a next-generation information society. To satisfy these requirements, we designed a novel high-electron mobility transistor (HEMT) structure employing wider bandgap AlGaN for a channel layer, which we called AlGaN channel HEMT, and investigated it. The wider bandgap is more effective for higher voltage operation of HEMTs and contributes to the increase of output power in RF power modules. As a result, fabricated AlGaN channel HEMTs had much higher breakdown voltages than those of conventional GaN channel HEMTs with good pinchoff operation and sufficiently high drain current density without noticeable current collapse. Furthermore, specific on-state resistances of fabricated AlGaN channel HEMTs were competitive with the best values of reported GaN- and SiC-based devices with similar breakdown voltages. These results indicate that the proposed AlGaN channel HEMTs are very promising not only for an information-communication society but also in the power electronics field.
    IEEE Transactions on Electron Devices 01/2013; 60(3):1046-1053. · 2.06 Impact Factor
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    ABSTRACT: The buffer layer in AlGaN channel HEMTs to suppress the off-state drain leakage current is investigated. By employing an AlN for the buffer layer in Al<sub>0.39</sub>Ga<sub>0.61</sub>N/Al<sub>0.16</sub>Ga<sub>0.84</sub>N HEMTs, the off-state drain leakage current was sufficiently suppressed and the breakdown voltage was enhanced. It was considered that employing the AlN for the buffer layer is important for extracting the superior material properties of the AlGaN in the channel layer.
    Electronics Letters 01/2010; · 1.04 Impact Factor
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    ABSTRACT: The fundamental device characteristics of AlGaN channel high electron mobility transistors formed on 4H-SiC and sapphire substrates are compared, and it is found that the drivability is apparently better for the SiC substrate. Judging from the simultaneous enhancement in mobility and the carrier concentration of the two-dimensional electron gases for the SiC substrate, the advantages of the SiC substrate originate from the excellent crystal quality of the AlGaN channel layer including the interface with the AlGaN barrier layer, which should be due to less lattice mismatch with the substrate.
    Electronics Letters 05/2009; · 1.04 Impact Factor
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    ABSTRACT: AlGaN/GaN high electron mobility transistors (HEMTs) with lightly doped drain (LDD) structures were fabricated using an Si ion implantation technique. The HEMTs show an obvious merit of enhancement of on-state breakdown voltage ( V <sub>br</sub>) of as high as 180 V, where that of a reference device without the LDD structure was 130 V. We also confirmed that resistance values at heavily doped drain regions were not changed by the introduction of the LDD structure.
    Electronics Letters 12/2008; · 1.04 Impact Factor
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    ABSTRACT: We demonstrated a remarkable breakdown voltage enhancement in a new high-electron-mobility transistor (HEMT) with a wider bandgap AlGaN channel layer. A Si ion implantation doping technique was utilized to achieve sufficiently low resistive source/drain contacts. The obtained maximum breakdown voltage was 1650 V with a gate-drain distance of 10 mum. This result is very promising for the further higher-power operation of high-frequency HEMTs.
    Electron Devices Meeting, 2007. IEDM 2007. IEEE International; 01/2008
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    ABSTRACT: We applied a Cat-CVD (catalytic chemical vapor deposition) passivation film to AlGaN/GaN HEMTs, to resolve the trade-off between their drain current transient time and gate-drain break down voltage. We did not employ any field plate because it degrades high frequency operation over C-band. The SiN passivation film, deposited after a NH<sub>3</sub> treatment, resulted in less transient time and less gate leakage current than conventional PE-CVD passivation. A T-shaped gate HEMT fabricated by this technique, with Lg = 0.4 μm and Wg = 50.4 mm, delivered an output power over 140 W (2.79 W/mm), which was a record power at C-band.
    Microwave Symposium Digest, 2005 IEEE MTT-S International; 07/2005
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    ABSTRACT: Recent progress in GaN based high electron mobility transistors (HEMTs) has revealed them to be strong candidates for future high power devices with high frequency operation. In order to extract and utilize the favorable GaN material properties, however, there is still a lot to be investigated. Reduction of the gate leakage current is one of the key issues to be solved for their further improvement. A high work function metal such as Pt, Ir, Pd or Mo was inserted to the conventional Ni/Au Schottky contact to n-GaN and AlGaN/GaN epilayers, and the Schottky diodes were studied in detail with respect to the thermal annealing in nitrogen ambient. The electrical characteristics were found to be changed by the thermal treatment in each device. A drastic improvement was attained in the Ni/Pt(Ir)/Au system whereas degradation occurred in Ni/Mo/Au by RTA at 500 °C for 5 min. These phenomena were confirmed to be dependent on the work function of each inserted metal. The role of Ni in the Ni/Pt/Au system was also investigated, and it was found to be essential in obtaining better electrical performance in comparison with the diodes without Ni, such as Pt/Au or Ir/Au Schottky electrodes. The AlGaN/GaN HEMTs were fabricated using Ni/Pt/Au gate contacts. Reduction of the gate leakage current by as much as four orders of magnitude was successfully recorded by thermal annealing without degrading the transconductance of the transistor, and it was concluded that this technique was promising for high power AlGaN/GaN HEMT electronics.
    Solid-State Electronics 05/2004; · 1.48 Impact Factor
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    ABSTRACT: Schottky diodes with Ni-Ti-Pt-Au Schottky electrodes on AlGaN-GaN heterostructures were fabricated and subjected to rapid thermal annealing. The electrical influence on them was investigated in terms of the existence of a thin Ni or Ti layer. The diodes of the Ni-Pt-Au system showed a drastic improvement in their electrical properties, such as an increase in the Schottky barrier height and a decrease in the leakage current, after the 600°C treatment whereas the thermal annealing effect was found to be small in the Ti-Pt-Au and the Pt-Au systems. The Ni was considered to play a significant role in realizing a clean Pt contact to AlGaN and reducing surface traps, which were revealed from Auger electron spectroscopy measurement and frequency-dependent capacitance-voltage measurement, respectively. The thermally-treated Ni-Pt-Au gate electrode was concluded to be practicable for realizing high performance HEMTs.
    IEEE Transactions on Electron Devices 04/2004; · 2.06 Impact Factor
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    ABSTRACT: A novel selective epitaxial growth (SEG) technology which combines low-temperature UHV-CVD and low-damage sidewall etch-back with a Cl<sub>2</sub>-plasma is experimentally demonstrated for elevated S/D ultra-thin SOI CMOS devices. It is found that the deviation of the parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI FETs can be nearly as low as that in bulk FETs because the excellent epi-Si surface morphology enables a uniform CoSi<sub>2</sub> film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results mean that this SEG technology is promising for elevated S/D ultra-thin SOI CMOS devices for the 90-nm technology node and beyond.
    Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on; 01/2003
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    ABSTRACT: A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect
    IEEE Transactions on Electron Devices 10/2001; · 2.06 Impact Factor
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    ABSTRACT: It is clearly demonstrated that source/drain (S/D) elevation is remarkably effective in suppressing the short channel effect against the shrinkage of gate sidewall spacers in MOSFETs. Even if the gate sidewall width is reduced to as very thin as 15 nm, the short channel effect is effectively suppressed by means of the highly elevated S/D regions (80 nm in the present case), though the characteristics of conventional MOSFETs are drastically degraded. This result is explained in terms of the fact that the serious influence due to the deep S/D implantation is suppressed by the formation of a quasi-single-drain configuration. Furthermore, the parasitic S/D resistance decrease, which will bring about drivability enhancement, was observed for reduction in the sidewall width. These favorable experimental results may indicate the definite necessity of elevated S/D engineering for future ultrashort MOSFETs.
    IEEE Electron Device Letters 08/2001; · 2.79 Impact Factor
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    ABSTRACT: Degradation of junction characteristics induced by STI stress has investigated in detail. STI stress is enhanced by the scaling of isolation pitch, the volume expansion induced by oxidation step, and the film stress of filling materials. The stress control becomes more important to keep the lower junction leakage current
    Junction Technology, 2001. IWJT. Extended Abstracts of the Second International Workshop on; 02/2001
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    ABSTRACT: A new fabrication process for realising T-shaped shallow trench isolation by the use of SiON spacers and liners is presented. This technique makes it possible to significantly increase the effective channel width of a metal oxide semiconductor field effect transistor (MOSFET), enhancing its drivability together with improving its subthreshold characteristics, without degrading fundamental isolation characteristics
    Electronics Letters 06/2000; · 1.04 Impact Factor
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    ABSTRACT: The gate length (L) dependence of the isolation edge effect is investigated for MOSFETs with various isolation structures. We extract the isolation edge effect for a single L by comparing with an H-shaped gate MOSFET which did not have any influence from the isolation edges. For shallow trench isolation (STI), the isolation edge effect is enhanced for L around the onset of the short channel effect (SCE) and is more prominent for a trench edge with a deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e., the bird's beak), the isolation edge effect operates in the opposite direction against the cases of STI, though it is enhanced around the SCE appearance point. The L dependence is successfully explained using the charge sharing model where the charge shared by the mixing effect between the SCE and the (inverse) narrow width effect [(I)NWE] is introduced at the channel corners. The enhancement of the isolation edge effect results from that the fraction of the charge shared by the mixing effect depends on L. In addition, the difference between STI and LOCOS occurs because the mixing effect for STI is opposite to that for LOCOS
    IEEE Transactions on Electron Devices 05/2000; · 2.06 Impact Factor
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    ABSTRACT: Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage.
    IEEE Electron Device Letters 01/2000; · 2.79 Impact Factor
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    ABSTRACT: Deep submicron MOSFETs with elevated source/drain (S/D) structures, where S/D extension regions were partially elevated besides deep S/D regions, were fabricated by use of Si selective epitaxial growth technique. As fairly compared with a well-developed conventional MOSFET, we clarify an advantage of the elevated S/D structures, i.e., improvement upon driving performance with keeping excellent short-channel characteristics, which is enhanced for decrease in gate sidewall spacer width. The experimental results are explained in terms of the reduction in S/D parasitic resistance by addition of the Si epitaxial layer where the impurity profile is suitable.
    IEEE Electron Device Letters 08/1999; · 2.79 Impact Factor
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    ABSTRACT: A low resistance salicided 0.1 μm CMOSFET has been developed with precisely controlled T-shaped gate and optimum gate structure for thick CoSi<sub>2</sub>. Selective Si growth (SSG) using a SiO<sub>2</sub>-SiN stacked sidewall with the exposed SiN top hill enables suppression of junction leakage for thick Co silicidation, to eliminate bridging between gate and source/drain (S/D), and to precisely control the extra gate length for T-shaped gates. Moreover, the nitrogen profile in the p<sup>+</sup> gate is optimized to suppress gate depletion induced by the thick Co. Since a heavily nitrided gate oxide insulator and N implantation of the poly-Si surface can prevent gate-implanted B ions from being diffused into the substrate and into the CoSi<sub>2</sub> layer, an increase in the gate sheet resistance, B penetration, and gate depletion can be simultaneously resolved, and thus high performance 0.1 μm CMOS can be achieved with gates of as low as 1.9 Ω/sq. sheet resistance
    VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on; 02/1999
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    ABSTRACT: A gate overlap length of only 16 nm between the gate and the source/drain has been achieved in fine n-type metal oxide semiconductor field effect transistors with 0.1 μm gate length by arsenic ion implantation through a thin oxide film formed by chemical vapour deposition. The presented technique enables the gate overlap length to be reduced by less than half of the value for conventional lower energy implantation while maintaining a shallow junction depth for the source/drain
    Electronics Letters 01/1999; · 1.04 Impact Factor
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    ABSTRACT: First Page of the Article
    VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on; 07/1997
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    ABSTRACT: Considerable reduction in the threshold voltage for sub-quarter-micron NMOSFETs can be achieved along with suppression of the short channel effects by only adding nitrogen implantation into the channel region. Moreover this simple process can improve hot carrier degradation. The superior performance is based on the effective acceptor concentration drop at the surface of the channel region as well as the light nitridation of the gate oxide and the side-wall spacer
    VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on; 07/1996