Jens Bargfrede

Infineon Technologies, München, Bavaria, Germany

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Publications (6)0 Total impact

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    ABSTRACT: The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very com- plex. Although it has been widely studied, it still lacks an effi- cient solution. As a result, state-of-the-art crosstalk calculators use simplistic and overly pessimistic models resulting in the over- estimation of crosstalk effects. Such pessimism in crosstalk analy- sis often leads to the triggering of false violations and consequently an inefficient use of design resources. The main contribution of this paper is a novel technique called Timing Arc Based Logic Analysis (TABLA) that serves as an effi- cient means to calculate realistic crosstalk bounds. TABLA uses timing arcs as basic elements to perform an efficient temporal logic analysis employing the min-max timing model using dedicated solvers for logic and timing. Additionally, a procedure to gener- ate powerful conflict clauses is proposed to improve the run time of the overall analysis. The proposed technique has been tested in an industrial environment on benchmark circuits as well as on an industrial design, and results are provided.
    2009 International Conference on Computer-Aided Design (ICCAD'09), November 2-5, 2009, San Jose, CA, USA; 01/2009
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    ABSTRACT: Accurate crosstalk analysis has become a key issue in static timing analysis of modern deep-submicron digital circuits. The inherent logic and timing properties of the circuit are often neglected in the crosstalk estimation process resulting in an overly pessimistic analysis. The problem of considering the logic correlations of the circuit to eliminate false crosstalk has been widely studied, but still lacks a very efficient solution also due to its NP-hard nature. In this paper, we propose a SAT solver based approach to efficiently solve the false crosstalk problem. We also propose a novel and very powerful bounding technique called adaptive bounding as well as an aggressor ordering technique called simple aggressor ordering for the branch and bound method running on top of the SAT solver. These techniques are proven to drastically increase the speed of false crosstalk analysis to an extent that nets with hundreds of aggressors can be handled. The results of this approach on the ISCAS89 benchmark circuits are provided.
    Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on; 04/2008
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    ABSTRACT: Accurate crosstalk analysis has become a key issue in Static Timing Analysis of modern deep–submicron digital circuits. The inherent logic and timing properties of the circuit are often neglected in the crosstalk estimation process resulting in an overly pessimistic analysis. The problem of considering the logic correlations of the??circuit to eliminate false crosstalk has been widely studied, but still lacks a very efficient solution also due to its NP–hard nature. In this paper, we propose a SAT solver based approach to efficiently solve the false crosstalk problem. We also propose a novel and very powerful bounding technique called Adaptive Bounding as well as an aggressor ordering technique called Simple Aggressor Ordering for the branch and bound method running on top of the SAT solver. These techniques are proven to drastically increase the speed of false crosstalk analysis to an extent that nets with hundreds of aggressors can be handled. The results of this approach on the ISCAS89 benchmark circuits are provided.
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    ABSTRACT: Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usually assume that the worst-case crosstalk occurs with all the aggressors of a victim (net or path) simultaneously inducing crosstalk even though this may not be possible at all. This overestimated crosstalk is called false noise. Logic correlations have been explored to reduce false noise in J.C. Beck, et al., (2004), which also used branch and bound method to solve the problem. In this paper, we propose a novel approach, named tendency graph approach (TGA), which preprocesses the logic constraints of the circuit to drastically speed up the fundamental branch and bound algorithm. The new approach has been implemented in C++ and tested on an industrial circuit in a current 90 nm technology, demonstrating that TGA considerably accelerates the solution to the false noise problem, and makes in many cases branch and bound feasible in the first place.
    Computer Design, 2006. ICCD 2006. International Conference on; 11/2007
  • Stefan Radtke, Jens Bargfrede, Walter Anheier
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    ABSTRACT: The generation of test patterns for digital circuits is known as an NP hard problem. Due to the backtracking mechanism in the sequential algorithms for test pattern generation it is difficult to speed up the process. In this paper we present a parallel formulation of the FAN algorithm implemented on a heterogeneous cluster of workstations. Two different methods are used to take into account easy- and hard-to-detect faults. We show the strategies for our parallel implementations as well as implementation details. Linear speedups are shown with the results. Furthermore we introduce a new method for test vector compaction using a genetic algorithm. This results in smaller test sets compared to traditional methods. The reader should be familiar with notations of the FAN algorithm
    1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings; 01/1995