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ABSTRACT: An accurate yield evaluation is essential in selecting redundancy allocation and testing strategies for memories. Yield evaluation can resolve the many issues revolving around cost-effective built-in self-test (BIST) and automatic test equipment (ATE)-based solutions for a higher test transparency. In this paper, two yield-calculation methodologies for SRAM arrays are proposed. General yield expressions for VLSI chips are initially presented. The regular and repetitive structure of an SRAM array is exploited, and substantial yield improvements can be achieved by the introduction of redundancy. Two repair yield-evaluation methods for one-dimensional redundant memory arrays are introduced and compared for ATE application. The first method is based on the sum of the probabilities of all repairable fault patterns; the second method is based on Markov modeling. Using industrial data, it is shown that these methods are applicable to ATE usage under different conditions of defect rate in the possible defects. Different features of the proposed methods are discussed
IEEE Transactions on Instrumentation and Measurement 11/2006; · 1.21 Impact Factor
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ABSTRACT: The objective of this paper is to provide a framework by which jitter phenomena, which are encountered at the output signals of a head board in an automatic test equipment (ATE), can be studied. In this paper, the jitter refers to the one caused by radiated electromagnetic interference (EMI) noise, which is present in the head of all ATE due to DC-DC converter activity. An initial analysis of the areas of the head board most sensitive to EMI noise has been made. It identifies a sensitive part in the loop filler of a phase locked loop which is used to obtain a high frequency clock for the timing generator. Different H-fields are then applied externally at the loop filter to verify the behavior of the output signal of the head board in terms of RMS jitter. As for RMS jitter measurements, a frequency domain methodology has been employed. A trend for RMS jitter variation with respect to radiated EMI magnitude as well as frequency has been obtained. Also the orientation of the external H-field source with respect to the target board and its effects on the measured RMS jitter has been investigated. For measuring the RMS value, a proper circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment.
Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE; 06/2004
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ABSTRACT: With the increasing needs for memory testing and repair, yield evaluation is an essential decision-making factor to define redundancy allocation and testing strategies. In particular, yield evaluation can resolve the many issues revolving around cost-effective BIST solutions and purely ATE based techniques to guarantee higher test transparency. In this document, two different yield calculation methodologies for SRAM arrays are presented. General yield calculation formulas for VLSI chips are initially presented. The regular repetitive structure of a RAM array is considered because it shows major yield improvements with the introduction of redundancy. Two repair yield evaluation formulas for a 1D redundant array are introduced and compared; the first one is based on Markov modeling, the second one is based on an approximation.
Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE; 06/2004
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ABSTRACT: Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures must be designed to facilitate this arrangement. An increase in ATE performance for scan test requires a reduction in both scan time and memory utilization as commonly used figures of merit; in this paper, an ATE hardware architecture that allows the scan test to be done in an "interleaved" mode (thus separating the Scan-In and Scan-Compare sequences), is utilized together with a novel test scheduling algorithm. Two variations of the algorithm which permit test reordering and merging as well as an efficient generation of the so-called monolithic test sequence are proposed. Scheduling is found in polynomial time complexity and the proposed approach resorts to heuristic conditions for merging the vectors. A substantial saving in both test time and memory is achieved.
Electronic Design, Test and Applications, 2004. DELTA 2004. Second IEEE International Workshop on; 02/2004
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ABSTRACT: This paper deals with the generation, measurement and modeling of the jitter encountered in the signals of a testhead board for automatic test equipment (ATE). A novel model is proposed for the jitter; this model takes into account the radiated electromagnetic interference (EMI) noise in the head of an ATE. The RMS value of the jitter is measured at the output signal of the testhead board to validate the proposed model. For measuring the RMS value, a novel circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment. An H-field is applied externally at the loop filter of a phase-locked loop (PLL), thus permitting the measurement of the RMS jitter to verify the transfer function between radiated EMI and jitter variation. The error between measured and predicted jitters is within a 15% level at both 200 kHz and 500 kHz.
IEEE Transactions on Instrumentation and Measurement 01/2004; · 1.21 Impact Factor
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ABSTRACT: Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16 A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.
Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on; 12/2003
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ABSTRACT: Recent research on modeling timing jitter has raised a requirement for a predictable, high magnitude, uniform, and wide bandwidth H-field. In this paper, a novel H-field generator design methodology is proposed. It consists of a single layer air core solenoid and a digital power switch driver that takes advantage of low power, wide bandwidth, and big current-driven capability. With input overdrive voltage, the digital switch can drive rail-to-rail voltage with output current up to 16A and power bandwidth more than 3 MHz. This paper demonstrates a novel solenoid driver circuit to generate an accurate H-field by comparing digital and analog approaches and comparing the experimental data with the theoretical data.
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 11/2003;
