Wei Wang

Publications (6)1.1 Total impact

• Source

  Available from: albany.edu

  Article: 3D Integration of CMOL Structures for FPGA Applications

  Z. Abid, Ming Liu, Wei Wang
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  ABSTRACT: In this paper, a novel 3D CMOS nanohybrid technology, 3D CMOL, is introduced to establish FPGA chips. By combining two leading technologies, hybrid CMOS/nanoelectronic circuit (CMOL) and 3D integration, 3D CMOL can provide a feasible and more efficient fabrication/assembly process than the existing 2D CMOL. Furthermore, 3D CMOL FPGA implements circuits in three dimensions so that it can increase the density of the nanodevices and achieve higher performance compared to 2D CMOL and field programmable nanowire interconnect (FPNI). This paper presents the architecture optimization, 3D integration, defect tolerance, and performance evaluation of 3D CMOL FPGA. It is expected that this technology can lead to technology breakthroughs towards the development of the next FPGA generation.
  IEEE Transactions on Computers 05/2011; · 1.10 Impact Factor
• Conference Proceeding: An efficient adaptive interlace-to-progressive scan conversion scheme and hardware implementation.

  Shahab Salehi, B. M. Handjojo, Wei Wang, Yaobin Chen
  International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece; 01/2006
• Conference Proceeding: Low-power FPGA implementation for DA-based video processing

  Z. Abid, Wei Wang, Yaobin Chen
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  ABSTRACT: In this paper, we propose a low-power distributed arithmetic (DA) -based method specifically for the field programmable field array (FPGA) implementation of video processing systems. By taking advantage of the correlation of the input data and using a parallel structure, the FPGA implementation of a convolution example based on the proposed method requires only 75% of power while maintaining the same throughput compared to the existing method of J.T. Ludwig, et al. (1996) and R. Amirtharajah, et al. (1999) . The proposed method can be applied to many video processing applications such as discrete cosine transform, discrete wavelet transform, discrete Fourier transform and motion estimation.
  VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on; 06/2005
• Conference Proceeding: New designs of 14-transistor PPM adder

  R. Mudassir, H. El-Razouk, Z. Abid, Wei Wang
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  ABSTRACT: In this paper, we propose improved designs of full adders, known as plus-plus-minus (PPM) adders, for redundant binary (RB) number systems applications. The proposed two PPM adder designs use 14 transistors and are derived from new algorithms. They achieve reduction in the time delay, power consumption, and chip area, compared to currently available designs. Furthermore, the proposed 14-transistor adders have been used to build two efficient designs of on-line radix-2 redundant multipliers. All the proposed designs have been implemented using 0.18 mum CMOS technology. The implementation results show that the proposed PPM adders have significant reduction in both power consumption and time delay compared to the 24-transistor PPM adder
  Electrical and Computer Engineering, 2005. Canadian Conference on; 06/2005
• Conference Proceeding: CRT-based three-prime RSA with immunity against hardware fault attack

  Yonghong Yang, Z. Abid, Wei Wang
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  ABSTRACT: In this paper, we carry out the study of the Chinese remainder theorem based three-prime RSA cryptosystem. The hardware fault attack on three-prime RSA cryptosystem is analyzed and it is proven that the three-prime RSA is more difficult to be broken than two-prime RSA by the hardware fault attack. Then, Shamir's checking procedure is extended from two-prime to three-prime RSA to increase its immunity against such attack. Finally an immune method for three-prime RSA without checking procedure is proposed in this paper, which is more efficient than the previous methods. It is expected that this proposed system will play an important role in the future cryptography applications.
  System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on; 08/2004
• Conference Proceeding: An Immune CRT-Based Three-prime RSA cryptosystem.

  Yonghong Yang, Zine-Eddine Abid, Wei Wang
  4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 15-16 September 2004, Chicago, IL, USA; 01/2004