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ABSTRACT: We have investigated the interfacial reaction between platinum and InGaP in a Schottky diode structure. There was a 7.5-nm-thick amorphous layer formed at the interface between Pt and InGaP after metal deposition. After annealing at 325 °C for 1 min, this amorphous layer increased to 12.8 nm and the reverse leakage current also decreased. The diffusion of Pt atoms and the crystallization of amorphous layer took place after annealing at 325 °C for 10 min. Prolonging the annealing to 3 h led to formation of Ga2Pt and GaPt3 phases in InGaP and Schottky diodes degraded after these new phases were observed.
Applied Physics Letters 02/2008; 92(8):082108-082108-3. · 3.84 Impact Factor
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ABSTRACT: An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degC for gate sinking. After the annealing, the device showed a positive threshold voltage (V<sub>th</sub>) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 muA/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the V<sub>th </sub> was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process
IEEE Electron Device Letters 03/2007; · 2.85 Impact Factor
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ABSTRACT: We have used proton and As/sup +/ implantation to increase the resistivity of conventional Si (10 /spl Omega/-cm) and Si-on-quartz substrates, respectively. A high resistivity of 1.6 M/spl Omega/-cm is measured that is close to intrinsic Si and semi-insulating GaAs. Very low loss and cross coupling of 6.3 dB/cm and -79 dB/cm (10 /spl mu/m gap) at 20 GHz are measured on these samples, respectively. The very high resistivity and improved rf performance are due to the extremely fast /spl sim/1 ps carrier lifetime stable even after a 400/spl deg/C annealing for 1 h. Little negative effect on gate oxide integrity is also observed as evidenced by the comparable stress-induced leakage current and charge-to-breakdown for 30 /spl Aring/ oxides.
IEEE Electron Device Letters 10/2000; · 2.85 Impact Factor
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ABSTRACT: We have used a simple process to fabricate Si/sub 0.3/Ge/sub 0.7//Si p-MOSFETs. The Si/sub 0.3/Ge/sub 0.7/ is formed using deposited Ge followed by 950/spl deg/C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm/sup 2//Vs is obtained from the Si/sub 0.3/Ge/sub 0.7/ p-MOSFET that is /spl sim/two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 /spl Aring/ Si/sub 0.3/Ge/sub 0.7/ thermal oxide grown at 1000/spl deg/C has a high breakdown field of 15 MV/cm, low interface trap density (D/sub it/) of 1.5/spl times/10/sup 11/ eV/sup -1/ cm/sup -2/, and low oxide charge of 7.2/spl times/10/sup 10/ cm/sup -2/. The source-drain junction leakage after implantation and 950/spl deg/C RTA is also comparable with the Si counterpart.
IEEE Electron Device Letters 08/2000; · 2.85 Impact Factor
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ABSTRACT: Electrical and reliability properties of ultrathin La/sub 2/O/sub 3/ gate dielectric have been investigated. The measured capacitance of 33 /spl Aring/ La/sub 2/O/sub 3/ gate dielectric is 7.2 /spl mu/F/cm/sup 2/ that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 /spl Aring/. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm/sup 2/ at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3/spl times/10/sup 10/ eV/sup -1//cm/sup 2/, and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO/sub 2/.
IEEE Electron Device Letters 08/2000; · 2.85 Impact Factor
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ABSTRACT: For thin oxides grown on high temperature formed Si/sub 0.3/Ge/sub 0.7/, the gate oxide quality is strongly dependent on oxide thickness and improves as thickness reduces from 50 to 30 /spl Aring/. The thinner 30 /spl Aring/ oxide has excellent quality as evidenced by the comparable leakage current, breakdown voltage, interface-trap density and charge-to-breakdown with conventional thermal oxide grown on Si. The achieved good oxide quality is due to the high temperature formed Si/sub 0.3/Ge/sub 0.7/ that is strain relaxed and stable during oxidation. The possible reason for strong thickness dependence may be due to the lower GeO/sub 2/ content formed in thinner 30 /spl Aring/ oxide rather than strain relaxation related rough surface or defects.
IEEE Electron Device Letters 07/2000; · 2.85 Impact Factor
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ABSTRACT: We have investigated the gate oxide integrity of thermal oxides direct grown on high temperature formed Si/sub 0.3/Ge/sub 0.7/. Good oxide integrity is evidenced by the low interface-trap density of 5.9/spl times/10/sup 10/ eV/sup -1/ cm/sup -2/, low oxide charge density of -5.6/spl times/10/sup 10/ cm/sup -2/, and the small stress-induced leakage current after -3.3 V stress for 10 000 s. The good gate oxide integrity is due to the high temperature formed and strain-relaxed Si/sub 0.3/Ge/sub 0.7/ that has a original smooth surface and stable after subsequent high temperature process.
IEEE Electron Device Letters 04/2000; · 2.85 Impact Factor
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ABSTRACT: The measured RF performance of 0.5, 0.25, and 0.18 μm MOSFETs
gradually saturates as scaling down occurs, which can be explained by
the derived analytical equation and simulation. The source-drain overlap
capacitance, C<sub>gd</sub>, and non-quasi-static effect are the main
factors but scale much slower than L<sub>g</sub>
Radio Frequency Integrated Circuits (RFIC) Symposium, 2000. Digest of Papers. 2000 IEEE; 02/2000
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ABSTRACT: We have achieved 1.6 MΩ-cm resistivity using ion
implantation that has little negative effect on MOS devices. Extremely
low loss and cross coupling of 6.3 and -79 dB/cm (10 μm gap) at 20
GHz are measured with 1 μm Al, respectively, which is due to implant
induced trap with ~1 ps carrier lifetime and stable to 400°C
Microwave Symposium Digest. 2000 IEEE MTT-S International; 02/2000
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ABSTRACT: High quality La<sub>2</sub>O<sub>3</sub> and Al<sub>2</sub>O<sub>3
</sub> are fabricated with EOT of 4.8 and 9.6 Å, leakage current
of 0.06 and 0.4 A/cm<sup>-2</sup> and D<sub>it</sub> of both 3×10
<sup>10</sup> eV<sup>-1</sup>/cm<sup>2</sup>, respectively. The high K
is further evidenced from high MOSFET's I<sub>d</sub> and g<sub>m</sub>
with low I<sub>OFF</sub>. Good SILC and Q<sub>BD</sub> are obtained and
comparable with SiO<sub>2</sub>. The low EOT is due to the high
thermodynamic stability in contact with Si and stable after
H<sub>2</sub> annealing up to 550°C
VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on; 02/2000
