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G. Bersuker,
D. Heh,
C.D. Young,
L. Morassi,
A. Padovani,
L. Larcher,
K.S. Yew, Y.C. Ong,
D.S. Ang,
K.L. Pey,
W. Taylor
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ABSTRACT: A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO<sub>2</sub> layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases.
Reliability Physics Symposium (IRPS), 2010 IEEE International; 06/2010
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G. Bersuker,
D. Heh,
C. D. Young,
L. Morassi,
A. Padovani,
L. Larcher,
K. S. Yew, Y. C. Ong,
D. S. Ang,
K. L. Pey,
W. Taylor
[show abstract]
[hide abstract]
ABSTRACT: A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO2 layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing SILC temperature dependency and its exponential increase from the fresh through soft and progressive breakdown phases
IEEE International Reliability Physics Symposium, Anaheim (CA), USA; 01/2010
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ABSTRACT: Through scanning tunneling microscopy, the rate of electrical stress induced trap generation in the vicinity of the tip/high- κ interface of the Sc <sub>2</sub> O <sub>3</sub>/ La <sub>2</sub> O <sub>3</sub>/ SiO <sub>x</sub> gate stack is observed to be much higher than that at the SiO <sub>x</sub>/ Si interface, implying that the former is more susceptible to electrical stress induced wear out. This polarity dependence is discussed in the context of current trap generation models and is shown to be best explained by anode hot-hole effect induced by inherently lower surface plasmon threshold energy at the metal/high- κ interface and a higher hole trapping rate in the relatively thick high- κ .
Applied Physics Letters 01/2009; · 3.84 Impact Factor
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ABSTRACT: The impact of nitrogen incorporation on the physical and electrical characteristics of the HfO <sub>2</sub> is examined. X-ray photoelectron spectroscopy shows that nitrogen can be incorporated into the HfO <sub>2</sub> via a two-step thermal anneal—first in ultrahigh vacuum (UHV) and subsequently in N <sub>2</sub> . Following the N <sub>2</sub> anneal, scanning tunneling microscopy in UHV reveals a marked reduction in the low-voltage leakage current under gate injection biasing. From band theory and existing first-principles simulation results, one may consistently attribute this improvement to the passivation of oxygen vacancies in the HfO <sub>2</sub> by nitrogen. Improvement in the breakdown strength of the HfO <sub>2</sub> subjected to ramp-voltage stress (substrate injection) is also observed after the N <sub>2</sub> anneal. The local current-voltage curves acquired concurrently during the ramp-voltage stress exhibit “space-charge limited conduction,” which implies that the observed improvement in breakdown strength may be related to a limitation of the current flow through the gate stack in the high stress voltage regime.
Journal of Applied Physics 10/2008; · 2.17 Impact Factor
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ABSTRACT: From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high- κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700 ° C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high- κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors.
Applied Physics Letters 06/2008; · 3.84 Impact Factor
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ABSTRACT: The tunneling current versus voltage characteristic of the Sc2O3/La2O3/SiOx high-κ gate stack is examined using scanning tunneling microscopy in ultrahigh vacuum. Different measurement bias polarities allow information on the location (i.e., in the high-κ or interfacial SiOx layer) of the electronic traps to be extracted. Two types of localized leakage sites may be distinguished. Lowering of the electron barrier height and trap-assisted tunneling are proposed as the two leakage mechanisms.
Applied Physics Letters 01/2008; 92(2):022904-022904-3. · 3.84 Impact Factor
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ABSTRACT: An advanced bilayer gate dielectric stack consisting of Sc2O3/La2O3/SiOx annealed in nitrogen at 300 °C was studied by scanning tunneling microscopy using bias dependent imaging. By changing the sample bias, electrical properties of different layers of the dielectric stack can be studied. At a sample bias of +3.5 V, the conduction band of the La2O3 layer is probed revealing a polycrystalline film with an average grain size of about 27 nm, in good agreement with that determined from planar transmission electron microscopy. High conductivity at grain boundaries, due possibly to dangling bonds, can be observed in this layer, as also observed in grain boundary assisted current conduction in metal-oxide-silicon structures. Imaging at a sample bias of −4 V probes the interfacial SiOx layer and an amorphouslike image of the interfacial layer is obtained.
Applied Physics Letters 09/2007; 91(10):102905-102905-3. · 3.84 Impact Factor
