Takeshi Yamamura

Fujitsu Ltd., Kawasaki Si, Kanagawa, Japan

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Publications (2)3.01 Total impact

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    ABSTRACT: We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-μm CMOS on a single test chip. The transceiver unit size was 1.6 mm × 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.
    IEEE Journal of Solid-State Circuits 01/2004; 38(12-38):2094 - 2100. DOI:10.1109/JSSC.2003.818577 · 3.01 Impact Factor
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    ABSTRACT: A quad 10Gb/s transceiver in 0.11μm CMOS communicates electric signals over balanced copper media. The transceiver uses a single 1.2V power supply and dissipates 415mW per channel. One PLL supplies a reference clock to two transmitter channels and two receiver channels. The transceiver contains analog front ends, clock recovery units, and 312MHz parallel interfaces.
    Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International; 02/2003